Extended voltage range coldspare tolerant off chip driver

Abstract

An off chip driver circuit includes a bias circuit and a driver sub-cell circuit. The bias circuit and off chip driver sub-cell circuit are in electrical communication with each other. The bias circuit includes two serially aligned diodes which are in an off-state when the driver sub-cell is in a functional mode and which are in an on-state when the driver sub-cell is in a cold spare mode. The arrangement of the diodes enables the off chip driver circuit to handle similar voltage signals in both the functional mode and the cold spare mode.

What is claimed: 
     
       1. A circuit comprising:
 a functional mode operating at a first voltage; and 
 a cold spare mode operating at the first voltage; 
 wherein the circuit supports and operates at the first voltage in both the functional mode and the cold spare mode. 
 
     
     
       2. The circuit of  claim 1 , further comprising:
 a bias circuit; and 
 an off chip driver sub-cell circuit, wherein the bias circuit is operatively coupled to the off chip driver sub-cell circuit and the bias circuit generates signals for cold spare voltage protection in the off chip driver. 
 
     
     
       3. The circuit of  claim 2 , wherein the bias circuit further comprises:
 a chip pad input/output (I/O) having a signal to be protected pass therethrough; 
 a first diode in electrical communication with the chip pad I/O; 
 a second diode in series with the first diode; 
 wherein the first and second diodes define a feedback voltage with the chip pad i/o to cause the circuit to be transparent in functional mode and operational in cold spare mode. 
 
     
     
       4. The circuit of  claim 3 , wherein the bias circuit further comprises:
 a first output (vir_vdd_io); 
 a second output (vir_vbias); 
 wherein the first output (vir_vdd_io) and second output (vir_vbias) are operatively connected to the off chip driver sub-cell circuit; 
 wherein when the bias circuit is in the functional mode, the first output (vir_vdd_io) equals a driver circuit power supply voltage (vdd_io) such that the first and second diodes are electrically transparent such that signals flow directly and uninterrupted from the driver circuit power supply voltage (vdd_io) to first output (vir_vdd_io). 
 
     
     
       5. The circuit of  claim 4 , wherein the bias circuit further comprises:
 a first p-channel field effect transistor (pFET) electrically coupled between the first output (vir_vdd_io) and the driver circuit power supply voltage (vdd_io) configured to be turned off in cold spare mode to pass voltage directly from the driver circuit power supply voltage (vdd_io) to the first output (vir_vdd_io). 
 
     
     
       6. The circuit of  claim 5 , wherein the first and second diodes siphons input voltage from the chip pad i/o in the cold spare mode. 
     
     
       7. The circuit of  claim 6 , wherein subtracting the second voltage from the first voltage is adapted to enable transistors to be stacked to support the similar voltage in the cold spare mode. 
     
     
       8. The circuit of  claim 7 , wherein the bias circuit further comprises:
 a bias voltage generated from the driver circuit power supply voltage (vdd_io) in functional mode and generated from the two series diodes in the ESD in cold spare mode, wherein the bias voltage is adapted to maintain other transistors below an operating voltage maximum for each of the other transistors while the total circuit operates at higher than the voltage maximum for each respective transistor. 
 
     
     
       9. The circuit of  claim 8 , wherein the bias circuit further comprises:
 an off-state and an on-state of the first and second diodes; 
 a threshold voltage of the first and second diodes, wherein when voltage from the chip pad I/O exceeds the threshold voltage, the first and second diodes are switched from the off-state to the on-state, and switching the first and second diodes from the off-state to the on-state switches the circuit from the functional mode to the cold spare mode. 
 
     
     
       10. The circuit of  claim 9 , wherein the bias circuit further comprises:
 wherein when the bias circuit is in cold spare mode, the voltage at the first output (vir_vdd_io) is two diode drops less than the voltage at the first output (vir_vdd_io) in functional mode, and the voltage at the second output (vir_vbias) is two diode drops less than the voltage at the second output (vir_vbias) in functional mode. 
 
     
     
       11. The circuit of  claim 10 , wherein the bias circuit does not affect functionality of the off chip driver sub-cell circuit in functional mode. 
     
     
       12. The circuit of  claim 11 , wherein the bias circuit further comprises:
 at least one resistor located intermediate the first input (vdd_io) and the first output (vir-vdd_io) to bleed voltage prior to the first output in the cold spare mode adapted to assist phantom powering of the first output (vir_vdd_io) in cold spare mode to prevent a build up of voltage over time. 
 
     
     
       13. The circuit of  claim 12 , wherein the bias circuit further comprises:
 a functional mode first voltage and the first input (vdd_io); 
 a functional mode second voltage at a second input (vbias); wherein the functional mode first and second voltages at the respective first and second inputs are different. 
 
     
     
       14. The circuit of  claim 13 , wherein the off chip driver sub-cell circuit further comprises:
 a first inverter having a first inverter input; 
 a second inverter having a second inverter input; 
 wherein the first and second inverters include stacked transistors adapted to operate at an extended voltage range; and 
 wherein the first and second inverter inputs receive one signal therethrough at different voltage levels, and the signal is sent through the first and second inverters to the chip pad I/O. 
 
     
     
       15. A method comprising:
 providing an off chip driver circuit that switches between a functional mode and a cold spare mode, wherein the off chip driver circuit supports similar voltage in both the functional mode and the cold spare mode; 
 passing supply and voltage protection signals through a bias circuit in the off chip drive circuit in the functional mode but passing voltages derived from a chip pad in the cold spare mode; and 
 receiving the voltage signals, in an off chip driver sub-circuit, from the off bias circuit. 
 
     
     
       16. The method of  claim 15 , further comprising:
 inputting a first voltage at a first input (vdd_io) and sending the first voltage towards a first output (vir_vdd_io); 
 subtracting a second voltage passing through at least two diodes from the first voltage from the first voltage to establish a third voltage; and 
 outputting the third voltage through the first output; 
 wherein subtracting the second voltage from the first voltage is adapted to enable transistors to be stacked to support the similar voltage in the cold spare mode. 
 
     
     
       17. The method of  claim 15 , further comprising:
 creating bias voltages by sending voltage through two series diodes; 
 applying the bias voltages to other transistors in the circuit, which is adapted to maintain the other transistors below an operating voltage maximum for each of the other transistors. 
 
     
     
       18. The method of  claim 16 , further comprising:
 in functional mode, generating the bias voltages directly from the first input (vdd_io); and 
 in cold spare mode, generating the bias voltages through two series diodes coupled with a chip pad input/output (I/O). 
 
     
     
       19. The method of  claim 15 , further comprising:
 switching the two series diodes from and off-state to an on-state when voltage across the two series diodes exceeds a threshold voltage; and 
 wherein switching the two series diodes from the off-state to the on-state switches the circuit from the functional mode to the cold spare mode; 
 bleeding voltage into the first output (vir_vdd_io) across the two series diodes from a chip pad input/output (I/O) in cold spare mode; 
 precluding voltage from bleeding voltage into the first output (I/O) so as to be functionally transparent in the functional mode. 
 
     
     
       20. The method of  claim 15 , further comprising:
 passing voltage from the first input to the first output without any effect from the two series diodes in functional mode; and 
 passing voltage from a second input (vbias) to a second output (vir_vbias) without any effect from the two series diodes in functional mode.