Current steering digital to analog converter with decoder free quad switching

Abstract

Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.

The invention claimed is: 
     
       1. A digital to analog converter, comprising:
 a first dynamic latch coupled to a first node to receive a data signal and coupled to a second node to receive an inverse of the data signal, the first dynamic latch being clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal; 
 a second dynamic latch coupled to the first node to receive the data signal and coupled to the second node to receive the inverse of the data signal, the second dynamic latch being clocked by an inverse of the clock signal and configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal; and 
 a quad switching bit cell configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching control signals; 
 wherein the quad switching bit cell includes first, second, third, and fourth transistors respectively controlled by the first, second, third, and fourth quad switching control signals; and 
 wherein the first, second, third, and fourth quad switching control signals are generated by the first and second dynamic latches such that one of the first, second, third, and fourth transistors is on while a remainder are off during each cycle of the clock signal. 
 
     
     
       2. The digital to analog converter of  claim 1 , wherein the quad switching bit cell comprises:
 a tail node; 
 first and second output nodes; 
 wherein the first transistor comprises a first p-channel transistor having a source coupled to the tail node, a drain coupled to the first output node, and a gate biased by the second quad switching control signal; 
 wherein the second transistor comprises a second p-channel transistor having a source coupled to the tail node, a drain coupled to the second output node, and a gate biased by the third quad switching control signal; 
 wherein the third transistor comprises a third p-channel transistor having a source coupled to the tail node, a drain coupled to the first output node, and a gate biased by the fourth quad switching control signal; and 
 wherein the fourth transistor comprises a fourth p-channel transistor having a source coupled to the tail node, a drain coupled to the second output node, and a gate biased by the first quad switching control signal. 
 
     
     
       3. The digital to analog converter of  claim 2 , wherein the first dynamic latch is in a reset phase when the clock signal is deasserted; and wherein the first and second quad switching control signals are asserted when the clock signal is deasserted, thereby resetting the first and fourth p-channel transistors when the first dynamic latch is in the reset phase. 
     
     
       4. The digital to analog converter of  claim 2 , wherein the second dynamic latch is in a reset phase when the inverse of the clock signal is deasserted; and wherein the third and fourth quad switching control signals are asserted when the inverse of the clock signal is deasserted, thereby resetting the second and third p-channel transistors when the second dynamic latch is in the reset phase. 
     
     
       5. The digital to analog converter of  claim 2 , further comprising a current source coupled to the tail node. 
     
     
       6. The digital to analog converter of  claim 1 , wherein the first dynamic latch comprises:
 a first p-channel transistor having a source coupled to a supply node, a drain coupled to a first node, and a gate biased by the clock signal; 
 a second p-channel transistor having a source coupled to the supply node, a drain coupled to the first node, and a gate biased by a second node; 
 a third p-channel transistor having a source coupled to the supply node, a drain coupled to the second node, and a gate biased by the first node; 
 a fourth p-channel transistor having a source coupled to the supply node, a drain coupled to the second node, and a gate biased by the clock signal; 
 a first n-channel transistor having a drain coupled to the first node, a source coupled to a third node, and a gate biased by the second node; 
 a second n-channel transistor having a drain coupled to the second node, a source coupled to a fourth node, and a gate biased by the first node; 
 a third n-channel transistor having a drain coupled to the third node, a source coupled to a fifth node, and a gate biased by the data signal; 
 a fourth n-channel transistor having a drain coupled to the fourth node, a source coupled to the fifth node, and a gate biased by the inverse of the data signal; 
 a fifth n-channel transistor having a drain coupled to the fifth node, a source coupled to ground, and a gate based by the clock signal. 
 
     
     
       7. The digital to analog converter of  claim 6 , wherein the first and second quad switching control signals are respectively generated at the first and second nodes. 
     
     
       8. The digital to analog converter of  claim 6 , wherein the third and fourth quad switching control signals are respectively generated at the third and fourth nodes. 
     
     
       9. The digital to analog converter of  claim 1 , wherein the second dynamic latch comprises:
 a first p-channel transistor having a source coupled to a supply node, a drain coupled to a first node, and a gate biased by the inverse of the clock signal; 
 a second p-channel transistor having a source coupled to the supply node, a drain coupled to the first node, and a gate biased by a second node; 
 a third p-channel transistor having a source coupled to the supply node, a drain coupled to the second node, and a gate biased by the first node; 
 a fourth p-channel transistor having a source coupled to the supply node, a drain coupled to the second node, and a gate biased by the inverse of the clock signal; 
 a first n-channel transistor having a drain coupled to the first node, a source coupled to a third node, and a gate biased by the second node; 
 a second n-channel transistor having a drain coupled to the second node, a source coupled to a fourth node, and a gate biased by the first node; 
 a third n-channel transistor having a drain coupled to the third node, a source coupled to a fifth node, and a gate biased by the data signal; 
 a fourth n-channel transistor having a drain coupled to the fourth node, a source coupled to the fifth node, and a gate biased by the inverse of the data signal; 
 a fifth n-channel transistor having a drain coupled to the fifth node, a source coupled to ground, and a gate based by the inverse of the clock signal. 
 
     
     
       10. A digital to analog converter, comprising:
 a first resettable differential latch coupled to a first node to receive a data signal and coupled to a second node to receive an inverse of the data signal, the first resettable differential latch configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal; 
 a second resettable differential latch coupled to a first node to receive the data signal and coupled to the second node to receive the inverse of the data signal, the second resettable differential latch configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal; 
 a quad switching converter controlled by the first, second, third, and fourth quad switching control signals and configured to generate an analog representation of the data signal; 
 wherein the quad switching converter includes first, second, third, and fourth transistors respectively controlled by the first, second, third, and fourth quad switching control signals; and 
 wherein the first, second, third, and fourth quad switching control signals are generated by the first and second resettable differential latches such that one of the first, second, third, and fourth transistors is on while a remainder are off during each cycle of the data signal. 
 
     
     
       11. The digital to analog converter of  claim 10 , wherein the first resettable differential latch comprises a first dynamic latch. 
     
     
       12. The digital to analog converter of  claim 10 , wherein the second resettable differential latch comprises a second dynamic latch. 
     
     
       13. The digital to analog converter of  claim 10 ,
 wherein the first and second transistors are configured to generate the analog representation of the data signal on first and second output nodes; and 
 wherein the first and second transistors are configured to be reset when the first resettable differential latch is reset. 
 
     
     
       14. The digital to analog converter of  claim 13 ,
 wherein the third and fourth transistors are configured to generate the analog representation of the data signal on the first and second output nodes; and 
 wherein the third and fourth transistors are configured to be reset when the second resettable differential latch is reset. 
 
     
     
       15. A method, comprising:
 receiving a data signal at a first resettable differential latch; 
 generating first and second quad switching control signals as a function of the data signal, using the first resettable differential latch; 
 receiving the data signal at a second resettable differential latch; 
 generating third and fourth quad switching control signals as a function of the data signal, using the second resettable differential latch; 
 generating an analog representation of the data signal using a quad switching digital to analog architecture as a function of the first, second, third, and fourth quad switching control signals by:
 resetting a first pair of transistors of a quad switching digital to analog architecture concurrently with resetting the first resettable differential latch, 
 resetting a second pair of transistors of the quad switching digital to analog architecture concurrently with resetting the second resettable differential latch, 
 generating the analog representation of the data signal by switching the second pair of transistors according to the third and fourth quad switching control signals while the first pair of transistors and first resettable differential latch are being reset, and 
 generating the analog representation of the data signal by switching the first pair of transistors according to the first and second quad switching control signals while the second pair of transistors and second resettable differential latch are being reset.