Method for generating a plurality of oscillating signals with different phases and associated circuit and local oscillator

Abstract

A circuit for generating a plurality of oscillating signals with different phases includes a frequency divider, a first delay chain, a second delay chain and a calibration circuit. The frequency divider is arranged for frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal. The first delay chain is arranged for delaying the first frequency-divided input signal, and the second delay chain is arranged for delaying the second frequency-divided input signal. The calibration circuit is arranged for controlling delay amounts of the first delay chain and the second delay chain according to signals within the first delay chain or the second delay chain; wherein output signals of a portion delay cells within the first delay chain and the second delay chain serve as the plurality of oscillating signals with different phases.

What is claimed is: 
     
       1. A circuit for generating a plurality of oscillating signals with different phases, comprising:
 a frequency divider, for frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal, wherein the first input signal and the second input signal have different phases; 
 a first delay chain comprising a plurality of first delay cells connected in series, for receiving the first frequency-divided input signal; 
 a second delay chain comprising a plurality of second delay cells connected in series, for receiving the second frequency-divided input signal; and 
 a calibration circuit, coupled to the first delay chain and the second delay chain, for controlling delay amounts of the first delay chain and the second delay chain according to signals within the first delay chain or the second delay chain; 
 wherein output signals of a portion of the first delay cells and the second delay cells serve as the plurality of oscillating signals with different phases; and the frequency divider has an odd divisor, and the plurality of oscillating signals are an in-phase signal, a quadrature signal, an inverted in-phase signal and an inverted quadrature signal. 
 
     
     
       2. The circuit of  claim 1 , wherein the output signals of two of the first delay cells serve as two of the in-phase signal, the quadrature signal, the inverted in-phase signal and the inverted quadrature signal, and the output signals of two of the second delay cells serve as the other two of the in-phase signal, the quadrature signal, the inverted in-phase signal and the inverted quadrature signal. 
     
     
       3. The circuit of  claim 1 , wherein each of the first delay cells and the second delay cells is an inverter. 
     
     
       4. The circuit of  claim 1 , wherein the calibration circuit controls the delay amounts of the first delay chain and the second delay chain by controlling a supply voltage of the first delay chain and the second delay chain. 
     
     
       5. The circuit of  claim 4 , wherein the calibration circuit generates two calibration signals to control a first supply voltage of the first delay chain and a second supply voltage of the second delay chain, respectively, to control the delay amounts of the first delay chain and the second delay chain. 
     
     
       6. The circuit of  claim 1 , wherein the calibration circuit controls the delay amounts of the first delay chain and the second delay chain by controlling currents of the first delay chain and the second delay chain. 
     
     
       7. The circuit of  claim 1 , wherein the calibration circuit controls the delay amounts of the first delay chain and the second delay chain by controlling loads of the first delay chain and the second delay chain. 
     
     
       8. The circuit of  claim 1 , wherein the calibration circuit generates at least one digital calibration signal to control the delay amounts of the first delay chain and the second delay chain. 
     
     
       9. The circuit of  claim 8 , wherein the calibration circuit comprises
 a logic circuit, for receiving part of the output signals of the first delay cells within the first delay chain and/or part of the output signals of the second delay cells within the second delay chain; 
 a low-pass filter, for filtering an output of the logic circuit to generate a filtered signal; and 
 an analog-to-digital converter, for converting the filtered signal to generate the at least one digital calibration signal. 
 
     
     
       10. A method for generating a plurality of oscillating signals with different phases, comprising:
 frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal, wherein the first input signal and the second input signal have different phases; 
 using a plurality of first delay cells connected in series to delay the first frequency-divided input signal; 
 using a plurality of second delay cells connected in series to delay the second frequency-divided input signal; 
 controlling delay amounts of the first delay cells and the second delay cells according to at least two outputs of the first delay cells or the second delay cells; and 
 outputting output signals of a portion of the first delay cells and the second delay cells to serve as the plurality of oscillating signals with different phases; 
 wherein the frequency dividing operation has an odd divisor, and the plurality of oscillating signals are an in-phase signal, a quadrature signal, an inverted in-phase signal and an inverted quadrature signal. 
 
     
     
       11. The method of  claim 10 , wherein output signals of two of the first delay cells serve as two of the in-phase signal, the quadrature signal, the inverted in-phase signal and the inverted quadrature signal, and outputs of two of the second delay cells serve as the other two of the in-phase signal, the quadrature signal, the inverted in-phase signal and the inverted quadrature signal. 
     
     
       12. The method of  claim 10 , wherein each of the first delay cells and the second delay cells is implemented by an inverter. 
     
     
       13. The method of  claim 10 , wherein the step of controlling the delay amounts of the first delay cells and the second delay cells comprises:
 controlling the delay amounts of the first delay cells and the second delay cells by controlling a supply voltage of the first delay cells and the second delay cells. 
 
     
     
       14. The method of  claim 13 , wherein the step of controlling the delay amounts of the first delay cells and the second delay cells comprises:
 generating two calibration signals to control a first supply voltage of the first delay cells and a second supply voltage of the second delay cells, respectively, to control the delay amounts of the first delay cells and the second delay cells. 
 
     
     
       15. The method of  claim 10 , wherein the step of controlling the delay amounts of the first delay cells and the second delay cells comprises:
 controlling the delay amounts of the first delay cells and the second delay cells by controlling currents of the first delay cells and the second delay cells. 
 
     
     
       16. The method of  claim 10 , wherein the step of controlling the delay amounts of the first delay cells and the second delay cells comprises:
 controlling the delay amounts of the first delay cells and the second delay cells by controlling loads of the first delay cells and the second delay cells. 
 
     
     
       17. The method of  claim 10 , wherein the step of controlling the delay amounts of the first delay cells and the second delay cells comprises:
 generating at least one digital calibration signal to control the delay amounts of the first delay cells and the second delay cells. 
 
     
     
       18. A circuit for generating a plurality of oscillating signals with different phases, comprising:
 a frequency divider, for frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal, wherein the first input signal and the second input signal have different phases; 
 a first delay chain comprising a plurality of first delay cells connected in series, for receiving the first frequency-divided input signal; 
 a second delay chain comprising a plurality of second delay cells connected in series, for receiving the second frequency-divided input signal; and 
 a calibration circuit, coupled to the first delay chain and the second delay chain, for controlling delay amounts of the first delay chain and the second delay chain according to signals within the first delay chain or the second delay chain; 
 wherein output signals of a portion of the first delay cells and the second delay cells serve as the plurality of oscillating signals with different phases; 
 wherein the calibration circuit controls the delay amounts of the first delay chain and the second delay chain by controlling a supply voltage of the first delay chain and the second delay chain, and the calibration circuit generates two calibration signals to control a first supply voltage of the first delay chain and a second supply voltage of the second delay chain, respectively, to control the delay amounts of the first delay chain and the second delay chain. 
 
     
     
       19. The circuit of  claim 18 , wherein the frequency divider has an odd divisor, and the plurality of oscillating signals are an in-phase signal, a quadrature signal, an inverted in-phase signal and an inverted quadrature signal. 
     
     
       20. The circuit of  claim 19 , wherein the output signals of two of the first delay cells serve as two of the in-phase signal, the quadrature signal, the inverted in-phase signal and the inverted quadrature signal, and the output signals of two of the second delay cells serve as the other two of the in-phase signal, the quadrature signal, the inverted in-phase signal and the inverted quadrature signal. 
     
     
       21. A circuit for generating a plurality of oscillating signals with different phases, comprising:
 a frequency divider, for frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal, wherein the first input signal and the second input signal have different phases; 
 a first delay chain comprising a plurality of first delay cells connected in series, for receiving the first frequency-divided input signal; 
 a second delay chain comprising a plurality of second delay cells connected in series, for receiving the second frequency-divided input signal; and 
 a calibration circuit, coupled to the first delay chain and the second delay chain, for controlling delay amounts of the first delay chain and the second delay chain according to signals within the first delay chain or the second delay chain; 
 wherein output signals of a portion of the first delay cells and the second delay cells serve as the plurality of oscillating signals with different phases; and the calibration circuit controls the delay amounts of the first delay chain and the second delay chain by controlling currents of the first delay chain and the second delay chain. 
 
     
     
       22. The circuit of  claim 21 , wherein the frequency divider has an odd divisor, and the plurality of oscillating signals are an in-phase signal, a quadrature signal, an inverted in-phase signal and an inverted quadrature signal. 
     
     
       23. The circuit of  claim 22 , wherein the output signals of two of the first delay cells serve as two of the in-phase signal, the quadrature signal, the inverted in-phase signal and the inverted quadrature signal, and the output signals of two of the second delay cells serve as the other two of the in-phase signal, the quadrature signal, the inverted in-phase signal and the inverted quadrature signal. 
     
     
       24. A circuit for generating a plurality of oscillating signals with different phases, comprising:
 a frequency divider, for frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal, wherein the first input signal and the second input signal have different phases; 
 a first delay chain comprising a plurality of first delay cells connected in series, for receiving the first frequency-divided input signal; 
 a second delay chain comprising a plurality of second delay cells connected in series, for receiving the second frequency-divided input signal; and 
 a calibration circuit, coupled to the first delay chain and the second delay chain, for controlling delay amounts of the first delay chain and the second delay chain according to signals within the first delay chain or the second delay chain; 
 wherein output signals of a portion of the first delay cells and the second delay cells serve as the plurality of oscillating signals with different phases; 
 wherein the calibration circuit generates at least one digital calibration signal to control the delay amounts of the first delay chain and the second delay chain, and the calibration circuit comprises 
 a logic circuit, for receiving part of the output signals of the first delay cells within the first delay chain and/or part of the output signals of the second delay cells within the second delay chain; 
 a low-pass filter, for filtering an output of the logic circuit to generate a filtered signal; and 
 an analog-to-digital converter, for converting the filtered signal to generate the at least one digital calibration signal. 
 
     
     
       25. The circuit of  claim 24 , wherein the frequency divider has an odd divisor, and the plurality of oscillating signals are an in-phase signal, a quadrature signal, an inverted in-phase signal and an inverted quadrature signal. 
     
     
       26. The circuit of  claim 25 , wherein the output signals of two of the first delay cells serve as two of the in-phase signal, the quadrature signal, the inverted in-phase signal and the inverted quadrature signal, and the output signals of two of the second delay cells serve as the other two of the in-phase signal, the quadrature signal, the inverted in-phase signal and the inverted quadrature signal.