US10172092B1ActiveUtility

Systems and methods for providing a sleep clock on a wireless communications device

94
Assignee: MARVELL INT LTDPriority: Jul 24, 2015Filed: Jun 27, 2016Granted: Jan 1, 2019
Est. expiryJul 24, 2035(~9 yrs left)· nominal 20-yr term from priority
H04W 52/0283H04W 52/0293H04L 7/0331H04L 7/0016H04W 52/0287G06F 1/08G06F 1/3237G06F 1/324G06F 1/32Y02D30/70Y02D10/00
94
PatentIndex Score
30
Cited by
2
References
14
Claims

Abstract

Example systems and methods are provided for maintaining a system clock during a sleep mode of a mobile communication device. An example system may include a high frequency clock circuit configured to generate a system clock, and a low frequency clock circuit configured to generate a sleep clock, where the sleep clock has a lower frequency than the system clock. The example system may further include a sleep system configured to deactivate the system clock in response to the mobile communication device entering sleep mode. The sleep system may include a sleep counter configured to use the sleep clock to maintain a sleep count for the deactivated system clock during the sleep mode, and a calibration unit configured to activate a calibration clock at periodic intervals during the sleep mode and utilize the calibration clock to calibrate a frequency of the sleep clock.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method for maintaining a system clock during a sleep mode of a mobile communication device, the method comprising:
 entering the sleep mode by the mobile communication device; 
 in response to entering the sleep mode, 
 deactivating the system clock, and 
 maintaining a sleep count for the deactivated system clock using a sleep clock, the sleep clock having a lower frequency than the system clock, wherein the sleep count is a number of sleep clock cycles that the mobile communication device is in the sleep mode; and 
 at periodic intervals throughout the sleep mode, 
 (a) activating a calibration clock, the calibration clock having a higher frequency than the sleep clock, 
 (b) using the calibration clock to calibrate a frequency of the sleep clock, and 
 (c) deactivating the calibration clock. 
 
     
     
       2. The method of  claim 1 , further comprising:
 exiting the sleep mode; and 
 in response to exiting the sleep mode, using the sleep count to determine a restoration value for setting the system clock. 
 
     
     
       3. The method of  claim 2 , further comprising:
 recording a value of the system clock in response to entering the sleep mode, 
 wherein the restoration value for the system clock is determined as a function of the recorded system clock value and the sleep count. 
 
     
     
       4. The method of  claim 1 , wherein the sleep clock is provided by a clock unit in a power management integrated circuit. 
     
     
       5. The method of  claim 1 , wherein a calibrated frequency (f′) of the sleep clock is determined according to an equation: 
       
         
           
             
               
                 
                   f 
                   ′ 
                 
                 = 
                 
                   1 
                   
                     
                       ( 
                       
                         
                           mx 
                           1 
                         
                         F 
                       
                       ) 
                     
                     n 
                   
                 
               
               , 
             
           
         
       
       where m is a number of periods of the calibration clock during a calibration interval, F is the frequency of the calibration clock, and n is a number of sleep clock counters. 
     
     
       6. The method of  claim 1 , wherein the calibration clock and system clock are both generated by a high frequency clock circuit. 
     
     
       7. A clock system for a mobile communication device, the clock system comprising:
 a high frequency clock circuit configured to generate a system clock; 
 a low frequency clock circuit configured to generate a sleep clock, the sleep clock having a lower frequency than the system clock; and 
 a sleep system stored on a computer readable medium and executed by one or more processors, the sleep system when executed being configured to deactivate the system clock in response to the mobile communication device entering a sleep mode, the sleep system including 
 a sleep counter configured to use the sleep clock to maintain a sleep count for the deactivated system clock during the sleep mode, wherein the sleep count is a number of sleep clock cycles that the mobile communication device is in the sleep mode, and 
 a calibration unit configured to, at periodic intervals throughout the sleep mode, (a) activate a calibration clock, (b) utilize the calibration clock to calibrate a frequency of the sleep clock, and (c) deactivate the calibration clock, 
 wherein the calibration clock has a higher frequency than the sleep clock. 
 
     
     
       8. The clock system of  claim 7 , wherein the sleep system is further configured to utilize the sleep count to determine a restoration value for setting the system clock in response to the mobile communication device exiting the sleep mode. 
     
     
       9. The clock system of  claim 8 , wherein the sleep system is further configured to record a value of the system clock in response to entering the sleep mode, and wherein the restoration value for the system clock is determined as a function of the recorded system clock value and the sleep count. 
     
     
       10. The clock system of  claim 7 , wherein the low frequency clock circuit is a clock unit in a power management integrated circuit. 
     
     
       11. The clock system of  claim 7 , wherein the calibration clock is generated by the high frequency clock circuit. 
     
     
       12. The clock system of  claim 11 , wherein the high frequency clock circuit is a phase locked loop circuit. 
     
     
       13. The clock system of  claim 7 , wherein the sleep clock is a 32 kHZ clock signal. 
     
     
       14. The clock system of  claim 7 , wherein a calibrated frequency (f′) of the sleep clock is determined according to an equation: 
       
         
           
             
               
                 
                   f 
                   ′ 
                 
                 = 
                 
                   1 
                   
                     
                       ( 
                       
                         
                           mx 
                           1 
                         
                         F 
                       
                       ) 
                     
                     n 
                   
                 
               
               , 
             
           
         
       
       where m is a number of periods of the calibration clock during a calibration interval, F is the frequency of the calibration clock, and n is a number of sleep clock counters.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.