Level shift circuit capable of reducing power consumption

Abstract

A level shift circuit receives an first input logic signal and a second input logic signal, and generates a first output logic signal and a second output logic signal. The level shift circuit includes a first current mirror module, a second current mirror module, and a latch module. The first current mirror module and the second current mirror module respectively output a first control logic signal having a phase performance following the first input logic signal and a second control logic signal having a phase performance following the second input logic signal. The latch module is coupled to the first current mirror module and the second current mirror module. The latch module receives the first control logic signal and the second control logic signal, and updates correspondingly and stores the output logic signal and the complementary output logic signal.

What is claimed is: 
     
       1. A level shift circuit configured to receive a first input logic signal and a second input logic signal, and generate a first output logic signal and a second output logic signal, and comprising:
 a first current mirror module configured to receive the first input logic signal and the second output logic signal, and output a first control logic signal having a phase performance following the first input logic signal; 
 a second current mirror module configured to receive the second input logic signal and the first output logic signal, and output a second control logic signal having a phase performance following the second input logic signal; and 
 a latch module coupled to the first current mirror module and the second current mirror module, and configured to receive the first control logic signal and the second control logic signal, update correspondingly and store the first output logic signal and the second output logic signal, the latch module comprising a first NOR gate and a second NOR gate, and the first NOR gate and the second NOR gate being cross-coupled. 
 
     
     
       2. The level shift circuit of  claim 1 , wherein:
 the first input logic signal and the second input logic signal are two complementary logic signals switching between a first high voltage level and a first low voltage level; and 
 the first output logic signal and the second output logic signal are two complementary logic signals switching between a second high voltage level and a second low voltage level. 
 
     
     
       3. The level shift circuit of  claim 2 , wherein the second high voltage level is higher than the first high voltage level. 
     
     
       4. The level shift circuit of  claim 1 , wherein the first current mirror module and the second current mirror module are activated at different periods. 
     
     
       5. The level shift circuit of  claim 1 , wherein:
 when the first input logic signal changes from a first low voltage level to a first high voltage level and the second input logic signal changes from the first high voltage level to the first low voltage level, the second output logic signal is kept at a second high voltage level initially so as to activate the first current mirror module and pull up the first control logic signal to the second high voltage level; and 
 when the first control logic signal is raised to the second high voltage level, the latch module is triggered and pulls down the second output logic signal to a second low voltage level. 
 
     
     
       6. The level shift circuit of  claim 5 , wherein:
 when the second output logic signal is pulled down to the second low voltage level, the latch module is triggered and pulls up the first output logic signal to the second high voltage level. 
 
     
     
       7. The level shift circuit of  claim 1 , wherein:
 the first NOR gate has a first input terminal configured to receive the first control logic signal, a second input terminal configured to receive the first output logic signal, and an output terminal configured to output the second output logic signal; and 
 the second NOR gate has a first input terminal configured to receive the second control logic signal, a second input terminal configured to receive the second output logic signal, and an output terminal configured to output the first output logic signal. 
 
     
     
       8. The level shift circuit of  claim 1 , wherein:
 the first current mirror module comprises a first switch disposed on a reference current path of the first current mirror module, and configured to activate the first current mirror module according to the second output logic signal; and 
 the second current mirror module comprises a second switch disposed on a reference current path of the second current mirror module, and configured to activate the second current mirror module according to the first output logic signal. 
 
     
     
       9. The level shift circuit of  claim 8 , wherein the first current mirror module comprises:
 a first transistor having a first terminal configured to receive a first system voltage, a second terminal coupled to the first switch, and a control terminal coupled to the second terminal of the first transistor; 
 a second transistor having a first terminal coupled to the first switch, a second terminal configured to receive a second system voltage, and a control terminal configured to receive the first input logic signal; and 
 a third transistor having a first terminal configured to receive the first system voltage, a second terminal configured to output the first control logic signal, and a control terminal coupled to the control terminal of the first transistor. 
 
     
     
       10. The level shift circuit of  claim 9 , wherein the first current mirror module further comprises:
 a fourth transistor having a first terminal coupled to the second terminal of the third transistor, a second terminal configured to receive the second system voltage, and a control terminal configured to receive the second input logic signal. 
 
     
     
       11. The level shift circuit of  claim 10 , wherein:
 the first system voltage is greater than the second system voltage; 
 the first transistor and the third transistor are P-type transistors; and 
 the second transistor and the fourth transistor are N-type transistors. 
 
     
     
       12. The level shift circuit of  claim 9 , wherein the first switch comprises a fifth transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the first terminal of the second transistor, and a control terminal configured to receive the second output logic signal. 
     
     
       13. The level shift circuit of  claim 12 , wherein the fifth transistor is an N-type transistor. 
     
     
       14. The level shift circuit of  claim 8 , wherein the second current mirror module comprises:
 a sixth transistor having a first terminal configured to receive a first system voltage, a second terminal coupled to the second switch, and a control terminal coupled to the second terminal of the sixth transistor; 
 a seventh transistor having a first terminal coupled to the second switch, a second terminal configured to receive a second system voltage, and a control terminal configured to receive the second input logic signal; and 
 an eighth transistor having a first terminal configured to receive the first system voltage, a second terminal configured to output the second control logic signal, and a control terminal coupled to the control terminal of the sixth transistor. 
 
     
     
       15. The level shift circuit of  claim 14 , wherein the second current mirror module further comprises:
 a ninth transistor having a first terminal coupled to the second terminal of the eighth transistor, a second terminal configured to receive the second system voltage, and a control terminal configured to receive the first input logic signal. 
 
     
     
       16. The level shift circuit of  claim 15 , wherein:
 the first system voltage is greater than the second system voltage; 
 the sixth transistor and the eighth transistor are P-type transistors; and 
 the seventh transistor and the ninth transistor are N-type transistors. 
 
     
     
       17. The level shift circuit of  claim 14 , wherein the second switch comprises a tenth transistor having a first terminal coupled to the second terminal of the sixth transistor, a second terminal coupled to the first terminal of the seventh transistor, and a control terminal configured to receive the first output logic signal. 
     
     
       18. The level shift circuit of  claim 17 , wherein the tenth transistor is an N-type transistor. 
     
     
       19. A level shift circuit configured to receive a first input logic signal and a second input logic signal, and generate a first output logic signal and a second output logic signal, and comprising:
 a first current mirror module configured to receive the first input logic signal and the second output logic signal, and output a first control logic signal having a phase performance following the first input logic signal; 
 a second current mirror module configured to receive the second input logic signal and the first output logic signal, and output a second control logic signal having a phase performance following the second input logic signal; and 
 a latch module coupled to the first current mirror module and the second current mirror module, and configured to receive the first control logic signal and the second control logic signal, update correspondingly and store the first output logic signal and the second output logic signal; 
 wherein: 
 the first current mirror module comprises:
 a first switch disposed on a reference current path of the first current mirror module, and configured to activate the first current mirror module according to the second output logic signal; 
 a first transistor having a first terminal configured to receive a first system voltage, a second terminal coupled to the first switch, and a control terminal coupled to the second terminal of the first transistor; 
 a second transistor having a first terminal coupled to the first switch, a second terminal configured to receive a second system voltage, and a control terminal configured to receive the first input logic signal; 
 a third transistor having a first terminal configured to receive the first system voltage, a second terminal configured to output the first control logic signal, and a control terminal coupled to the control terminal of the first transistor; and 
 a first resistor having a first terminal coupled to the second terminal of the third transistor, and a second terminal configured to receive the second system voltage; and 
 
 the second current mirror module comprises a second switch disposed on a reference current path of the second current mirror module, and configured to activate the second current mirror module according to the first output logic signal. 
 
     
     
       20. A level shift circuit configured to receive a first input logic signal and a second input logic signal, and generate a first output logic signal and a second output logic signal, and comprising:
 a first current mirror module configured to receive the first input logic signal and the second output logic signal, and output a first control logic signal having a phase performance following the first input logic signal; 
 a second current mirror module configured to receive the second input logic signal and the first output logic signal, and output a second control logic signal having a phase performance following the second input logic signal; and 
 a latch module coupled to the first current mirror module and the second current mirror module, and configured to receive the first control logic signal and the second control logic signal, update correspondingly and store the first output logic signal and the second output logic signal; 
 wherein: 
 the first current mirror module comprises a first switch disposed on a reference current path of the first current mirror module, and configured to activate the first current mirror module according to the second output logic signal; and 
 the second current mirror module comprises:
 a second switch disposed on a reference current path of the second current mirror module, and configured to activate the second current mirror module according to the first output logic signal; 
 a sixth transistor having a first terminal configured to receive a first system voltage, a second terminal coupled to the second switch, and a control terminal coupled to the second terminal of the sixth transistor; 
 a seventh transistor having a first terminal coupled to the second switch, a second terminal configured to receive a second system voltage, and a control terminal configured to receive the second input logic signal; 
 an eighth transistor having a first terminal configured to receive the first system voltage, a second terminal configured to output the second control logic signal, and a control terminal coupled to the control terminal of the sixth transistor; and 
 a second resistor having a first terminal coupled to the second terminal of the eighth transistor, and a second terminal configured to receive the second system voltage.