Bank interleaving controller and semiconductor device including the same

Abstract

A bank interleaving controller may include a power calculator and a write driver. The power calculator may calculate a total power consumption by adding a power consumption of one or more memory banks that are performing write operations and an amount of power that is expected to be additionally consumed to write input data. The write driver may write the input data to a memory cell corresponding to an input address when the total power consumption is equal to or less than a reference power consumption.

What is claimed is: 
     
       1. A bank interleaving controller comprising:
 a power calculator configured to calculate a total power consumption by adding a power consumption of one or more memory banks that are performing write operations and an amount of power that is expected to be additionally consumed to write input data; and 
 a write driver configured to write the input data to a memory cell corresponding to an input address when the total power consumption is equal to or less than a reference power consumption. 
 
     
     
       2. The bank interleaving controller according to  claim 1 , wherein the power calculator compares data bits of the input data to corresponding data bits of old data previously stored in the memory cell corresponding to the input address, and calculates an amount of power expected to be consumed when a write operation is performed only on data bits that are different from those of the old data to obtain the amount of power that is expected to be additionally consumed. 
     
     
       3. The bank interleaving controller according to  claim 2 , wherein the write driver performs a write operation only on the data bits that are different from those of the old data, among the bits of the input data. 
     
     
       4. The bank interleaving controller according to  claim 2 , further comprising a data reader configured to read the old data stored in the memory cell corresponding to the input address. 
     
     
       5. The bank interleaving controller according to  claim 1 , further comprising a decision circuit configured to determine whether the total power consumption is equal to or less than the reference power consumption. 
     
     
       6. The bank interleaving controller according to  claim 5 , wherein the decision circuit enables a write enable signal when the total power consumption is equal to or less than the reference power consumption. 
     
     
       7. The bank interleaving controller according to  claim 6 , wherein the write driver writes the input data to the memory cell corresponding to the input address in response to the write enable signal. 
     
     
       8. The bank interleaving controller according to  claim 1 , further comprising a delay calculator configured to calculate a point in time when the write operation of the memory bank that started the write operation first is ended, among the one or more memory banks that are performing their write operations, when the total power consumption is larger than the reference power consumption. 
     
     
       9. The bank interleaving controller according to  claim 8 , wherein the power calculator waits until the point in time calculated by the delay calculator, and then updates the total power consumption by subtracting a power consumption of the memory bank that has completed its write operation from the total power consumption. 
     
     
       10. The bank interleaving controller according to  claim 9 , wherein the write driver writes the input data to the memory cell corresponding to the input address when the updated total power consumption is equal to or smaller than the reference power consumption. 
     
     
       11. A semiconductor device comprising:
 a memory cell array divided into a plurality of banks; and 
 a bank interleaving controller configured to store data in the plurality of banks, 
 wherein the bank interleaving controller comprises: 
 a power calculator configured to calculate a total power consumption by adding a power consumption of one or more banks that are performing write operations and an amount of power that is expected to be additionally consumed to write input data; and 
 a write driver configured to write the input data to a memory cell corresponding to an input address when the total power consumption is equal to or less than a reference power consumption. 
 
     
     
       12. The semiconductor device according to  claim 11 , wherein the power calculator compares data bits of the input data to corresponding data bits of old data previously stored in the memory cell corresponding to the input address, and calculates an amount of power expected to be consumed when a write operation is performed only on data bits that are different from those of the old data to obtain the amount of power that is expected to be additionally consumed. 
     
     
       13. The semiconductor device according to  claim 12 , wherein the write driver performs a write operation only on the data bits that are different from those of the old data, among the bits of the input data. 
     
     
       14. The semiconductor device according to  claim 11 , wherein the bank interleaving controller further comprises a data reader configured to read the old data stored in the memory cell corresponding to the input address. 
     
     
       15. The semiconductor device according to  claim 11 , wherein the bank interleaving controller further comprises a decision circuit configured to decide whether the total power consumption is equal to or less than the reference power consumption. 
     
     
       16. The semiconductor device according to  claim 15 , wherein the decision circuit enables a write enable signal when the total power consumption is equal to or less than the reference power consumption. 
     
     
       17. The semiconductor device according to  claim 16 , wherein the write driver writes the input data to the memory cell corresponding to the input address in response to the write enable signal. 
     
     
       18. The semiconductor device according to  claim 11 , wherein the bank interleaving controller further comprises a delay calculator configured to calculate a point in time when the write operation of the bank that started the write operation first, among the one or more banks that are performing their write operations, when the total power consumption is larger than the reference power consumption. 
     
     
       19. The semiconductor device according to  claim 18 , wherein the power calculator waits until the point in time calculated by the delay calculator, and then updates the total power consumption by subtracting a power consumption of the bank that has completed its write operation from the total power consumption. 
     
     
       20. The semiconductor device according to  claim 19 , wherein when the write driver writes the input data to the memory cell corresponding to the input address when the updated total power consumption is equal to or smaller than the reference power consumption.