Lithium-drift based resistive processing unit for accelerating machine learning training

Abstract

Resistive processing unit including: a plurality of transistors each having a lithium-doped region, wherein the plurality of transistors are arranged in an array to provide resistance; at least one first transmission line electrically connected to a source region of each transistor in at least one column of the array; at least one second transmission line electrically connected to a drain region of each transistor in at least one row of the array; and at least one third transmission line electrically connected to a gate region of the plurality of transistors in at least one row of the array; wherein application of an electrical voltage to the at least one first transmission line, the at least one second transmission line or the at least one third transmission line mobilizes lithium ions in the lithium region, thereby affecting a channel resistance of at least one transistor in the plurality of transistors.

What is claimed is: 
     
       1. A resistive processing unit, comprising:
 a plurality of transistors each having at least one lithium-doped region, wherein the plurality of transistors are arranged in an array to provide resistance; 
 at least one first transmission line electrically connected to a source region of each transistor in at least one column of the array; 
 at least one second transmission line electrically connected to a drain region of each transistor in at least one row of the array; and 
 at least one third transmission line electrically connected to a gate region of the plurality of transistors in at least one row of the array; 
 wherein application of an electrical voltage to the at least one first transmission line, the at least one second transmission line or the at least one third transmission line mobilizes lithium ions in the lithium region, thereby affecting a channel resistance of at least one transistor in the plurality of transistors. 
 
     
     
       2. The system of  claim 1 , wherein the at least one lithium-doped region is located in a channel of each transistor in the plurality of transistors. 
     
     
       3. The system of  claim 1 , wherein the at least one lithium-doped region is located in the source and the drain of each transistor in the plurality of transistors. 
     
     
       4. The system of  claim 1 , wherein each transistor in the plurality of transistors further comprises:
 a silicon germanium (SiGe) region. 
 
     
     
       5. The system of  claim 4 , wherein the SiGe region is located in at least one of: the channel of each transistor and the source and drain of each transistor. 
     
     
       6. The system of  claim 1 , wherein each transistor in the plurality of transistors further comprises:
 a substrate contact, wherein the substrate contact of each transistor in the plurality of transistors is electrically connected via a fourth transmission line. 
 
     
     
       7. The system of  claim 6 , wherein application of an electrical voltage to the fourth transmission line mobilizes lithium ions in the lithium-doped region, thereby affecting a channel resistance of a transistor in the plurality of transistors. 
     
     
       8. The system of  claim 1 , wherein the structure of each transistor in the plurality of transistors is a planar field effect transistor. 
     
     
       9. The system of  claim 1 , wherein the structure of each transistor in the plurality of transistors is a fin field effect transistor. 
     
     
       10. The system of  claim 1 , wherein the structure of each transistor in the plurality of transistors is a polysilicon thin film transistor. 
     
     
       11. The system of  claim 1 , wherein the structure of each transistor in the plurality of transistors is an amorphous silicon thin film transistor. 
     
     
       12. The system of  claim 1 , wherein the structure of each transistor in the plurality of transistors is a poly-germanium thin film transistor. 
     
     
       13. The system of  claim 1 , wherein the structure of each transistor in the plurality of transistors is an amorphous germanium thin film transistor. 
     
     
       14. A method for forming a resistive processing unit, comprising:
 forming a plurality of transistors arranged in an array having a plurality of columns and a plurality of rows, each transistor having a source region, a drain region, a gate region, wherein at least one region includes a lithium-doped region therein; 
 forming at least one first transmission line for electrically connecting the source region of each transistor in at least one column of the plurality of columns in the array; 
 forming at least one second transmission line for electrically connecting the drain region of each transistor in at least one row of the plurality of rows in the array; and 
 forming at least one third transmission line for electrically connecting the gate region of each transistor in at least one row of the plurality of rows in the array; 
 wherein upon applying an electrical voltage to the at least one first transmission line, the at least one second transmission line or the at least one third transmission line, the electrical voltage mobilizes lithium ions in the lithium-doped region, thereby affecting a channel resistance of at least one transistor in the plurality of transistors. 
 
     
     
       15. The method of  claim 14 , wherein forming the lithium-doped region of each transistor further comprises:
 forming the lithium-doped region in a channel of each transistor in the plurality of transistors. 
 
     
     
       16. The method of  claim 14 , wherein forming the lithium-doped region of each transistor further comprises:
 forming the lithium-doped region in the source and the drain of each transistor in the plurality of transistors. 
 
     
     
       17. The method of  claim 14 , further comprising:
 forming a silicon germanium (SiGe) region for each transistor in the plurality of transistors. 
 
     
     
       18. The method of  claim 17 , wherein forming the SiGe is in at least one of: the channel of each transistor and the source and drain of each transistor. 
     
     
       19. The method of  claim 14 , further comprising:
 forming a substrate contact for each transistor in the plurality of transistors; and 
 forming at least one fourth transmission line electrically connecting the substrate contact of each transistor in at least one column of the array. 
 
     
     
       20. The method of  claim 19 , wherein applying an electrical voltage to the fourth transmission line mobilizes lithium ions in the lithium-doped region, thereby affecting a channel resistance of a transistor in the plurality of transistors.