Methods and apparatus for synchronizing communication with a memory controller

Abstract

A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.

What is claimed is: 
     
       1. An integrated-circuit device comprising:
 a data transmitter having a data input to receive a data input signal, a timing input to receive a timing signal, and a data output to transmit a data output signal timed to the timing signal; 
 a strobe transmitter to transmit a transmit-strobe signal synchronized with the timing signal; and 
 a phase-control circuit to control a phase of the timing signal and the transmit-strobe signal, the phase-control circuit including:
 memory to store at least one transmit state setting the phase of the timing signal and the transmit-strobe signal. 
 
 
     
     
       2. The integrated-circuit device of  claim 1 , further comprising a phase detector to detect a phase of a receive-timing signal. 
     
     
       3. The integrated-circuit device of  claim 2 , the phase-control circuit to derive a receive state from the detected phase of the receive-timing signal. 
     
     
       4. The integrated-circuit device of  claim 3 , the phase-control circuit to store the receive state absent the receive-timing signal. 
     
     
       5. The integrated-circuit device of  claim 3 , the phase-control circuit to derive the transmit state from the receive state. 
     
     
       6. The integrated-circuit device of  claim 5 , wherein deriving the transmit state from the receive state comprises subtracting the receive state from unity. 
     
     
       7. The integrated-circuit device of  claim 2 , wherein the receive-timing signal is a data strobe. 
     
     
       8. The integrated-circuit device of  claim 1 , wherein the receive-timing signal transitions irregularly between relatively high and low voltage levels. 
     
     
       9. The integrated-circuit device of  claim 1 , further comprising a first integrated circuit to receive the data output signal and the transmit-strobe signal, the at least one transmit state comprising a first transmit state to time the data output signal to the first integrated circuit. 
     
     
       10. The integrated-circuit device of  claim 9 , further comprising a second integrated circuit, the at least one transmit state comprising a second transmit state to time second output data transmitted to the second integrated circuit. 
     
     
       11. A method of communicating a transmit data signal with a timing-reference signal timed to the transmit data signal, the method comprising:
 deriving a receive state from a timing-reference signal accompanying a received data signal; 
 deriving a transmit state from the receive state; 
 storing at least one of the receive state and the transmit state; 
 phase adjusting a transmit data signal responsive to the transmit state; and 
 storing the transmit state absent the transmit data signal. 
 
     
     
       12. The method of  claim 11 , further comprising phase adjusting a second timing-reference signal responsive to the transmit state and transmitting the second timing-reference signal with the transmit data signal. 
     
     
       13. The method of  claim 12 , further comprising phase adjusting the second timing-reference signal ninety degrees out of phase with respect to the transmit data signal. 
     
     
       14. The method of  claim 11 , wherein deriving the transmit state from the receive state comprises subtracting the receive state from unity. 
     
     
       15. The method of  claim 11 , wherein the timing-reference signal is a data strobe. 
     
     
       16. The method of  claim 11 , wherein the timing-reference signal transitions irregularly between relatively high and low voltage levels. 
     
     
       17. The method of  claim 11 , further comprising:
 deriving a second receive state from a second timing-reference signal accompanying a second received data signal; 
 deriving a second transmit state from the second receive state; 
 storing at least one of the second receive state and the second transmit state absent the second received data signal; and 
 phase adjusting a second transmit data signal responsive to the second transmit state. 
 
     
     
       18. An integrated circuit device comprising:
 a data transmitter having a data input to receive a data input signal, a timing input to receive a timing signal, and a data output to transmit a data output signal timed to the timing signal; 
 means for deriving a receive state from a timing-reference signal accompanying a received data signal; 
 memory for storing the receive state absent the received data signal; 
 means for deriving a transmit state from the receive state; and 
 means for phase adjusting a transmit data signal responsive to the transmit state. 
 
     
     
       19. The integrated circuit device of  claim 18 , further comprising means for storing the transmit state.