Phased array with beamforming integrated circuit having two signal chains

Abstract

A beamforming integrated circuit has a single channel with a transmit chain and a receive chain. The transmit chain is configured to transmit an output signal and, in a corresponding manner, the receive chain is configured to receive an input signal. The integrated circuit also has separate horizontal and vertical polarity ports, and a double pole, double throw switch operably coupled between the chains and the ports. The double pole, double throw switch is configured to switch between operation in a first mode and a second mode.

What is claimed is: 
     
       1. A beamforming integrated circuit comprising:
 a transmit vector modulator configured to receive control signals from an antenna controller and to generate an output signal that contributes to a beam, wherein a signal amplitude and phase of the output signal are based on the control signals; 
 a single channel having a transmit chain and a receive chain, the transmit chain configured to transmit the output signal, the receive chain configured to receive an input signal; 
 a horizontal polarity port; 
 a vertical polarity port; and 
 a double pole, double throw switch operably coupled between the chains and the ports, the double pole, double throw switch being configured to switch between operation in a first mode and a second mode, 
 the double pole, double throw switch in the first mode being configured to couple the transmit chain to one of the horizontal polarity port and the vertical polarity port, 
 the double pole, double throw switch in the second mode configured to couple the receive chain to the other of the horizontal polarity port and the vertical polarity port not coupled with the transmit chain in the first mode, 
 the transmit chain being electrically isolated from the receive chain in the first and second modes. 
 
     
     
       2. The beamforming integrated circuit as defined by  claim 1  further comprising a die substrate, at least a portion of the transmit chain and the receive chain being implemented by the die substrate. 
     
     
       3. The beamforming integrated circuit as defined by  claim 2  wherein the die substrate comprises a silicon-on-insulator wafer having a device layer and a handle layer, the at least a portion of the transmit chain and the receive chain being implemented on the device layer. 
     
     
       4. The beamforming integrated circuit as defined by  claim 2  wherein the die substrate includes at least one flip chip interface configured for flip chip bonding. 
     
     
       5. The beamforming integrated circuit as defined by  claim 1  wherein the transmit chain and receive chain each include a plurality of circuit blocks, the integrated circuit being configured to activate and deactivate selected circuit blocks in each of the chains. 
     
     
       6. The beamforming integrated circuit as defined by  claim 1  wherein the transmit chain includes a power amplifier and a transmit phase shifter, the receive chain including a low noise amplifier and a receive phase shifter. 
     
     
       7. The beamforming integrated circuit as defined by  claim 6  wherein the receive chain includes a receive chain input selectively couplable with the double pole, double throw switch, the receive chain also including a digital step attenuator and a buffer amplifier between the receive phase shifter and the digital step attenuator. 
     
     
       8. The beamforming integrated circuit as defined by  claim 6  wherein the transmit chain includes a transmit chain output selectively couplable with the double pole, double throw switch, the transmit chain also including a digital step attenuator and a buffer amplifier between the transmit phase shifter and the digital step attenuator. 
     
     
       9. The beamforming integrated circuit as defined by  claim 1  wherein the double pole, double throw switch in the first mode is configured to couple the transmit chain to of the horizontal polarity port, further wherein the double pole, double throw switch in the second mode is configured to couple the receive chain to the vertical polarity port. 
     
     
       10. The beamforming integrated circuit as defined by  claim 1  wherein the double pole, double throw switch in the first mode is configured to couple the transmit chain to of the vertical polarity port, further wherein the double pole, double throw switch in the second mode is configured to couple the receive chain to the horizontal polarity port. 
     
     
       11. The beamforming integrated circuit as defined by  claim 1  wherein the double pole, double throw switch is configured to prevent simultaneous signal receipt by the receive chain and signal transmission by the transmit chain. 
     
     
       12. A phased array comprising:
 a laminar substrate; 
 a plurality of elements on the laminar substrate forming a patch phased array, each of the elements including both an element horizontal polarity port and an element vertical polarity port; and 
 a plurality of beamforming integrated circuits on the laminar substrate, each of the plurality of beamforming integrated circuits comprising: 
 a transmit chain and a receive chain, the transmit chain configured to transmit an output signal, the receive chain configured to receive an input signal; 
 an IC horizontal polarity port and an IC vertical polarity port; and 
 a double pole, double throw switch operably coupled between the chains and the IC ports, the double pole, double throw switch being configured to switch between operation in a first mode and a second mode, 
 the double pole, double throw switch in the first mode being configured to couple the transmit chain to one of the IC horizontal polarity port and the IC vertical polarity port, 
 the double pole, double throw switch in the second mode configured to couple the receive chain to the other of the IC horizontal polarity port and the IC vertical polarity port not coupled with the transmit chain in the first mode, 
 each IC horizontal polarity port being electrically connected with one element horizontal polarity port, 
 each IC vertical polarity port being electrically connected with one element vertical polarity port. 
 
     
     
       13. The phased array as defined by  claim 12  wherein each beamforming integrated circuit is flip-chip mounted to the laminar substrate. 
     
     
       14. The phased array as defined by  claim 12  wherein each beamforming integrated circuit is coupled with no more than one element. 
     
     
       15. The phased array as defined by  claim 12  wherein each beamforming integrated circuit further comprises a silicon-on-insulator die substrate having a device layer and a handle layer, at least a portion of the transmit chain and the receive chain being implemented by the device layer. 
     
     
       16. The phased array as defined by  claim 12  wherein for each beamforming integrated circuit, the transmit chain and receive chain each includes a plurality of circuit blocks, each beamforming integrated circuit being configured to activate and deactivate selected circuit blocks in each of the chains. 
     
     
       17. A beamforming integrated circuit comprising:
 a die substrate having (1) a transmit vector modulator configured to receive control signals from an antenna controller and to generate an output signal that contributes to a beam, wherein a signal amplitude and phase of the output signal are based on the control signals, (2) a transmit chain configured to transmit the output signal, and (3) a receive chain; 
 a first port having a first polarity; 
 a second port having a second polarity, the first polarity being substantially orthogonal to the second polarity; and 
 a double pole, double throw switch operably coupled between the chains and the ports, the double pole, double throw switch being configured to switch between operation in a first mode and a second mode, 
 the double pole, double throw switch in the first mode being configured to couple the transmit chain to the first port, 
 the double pole, double throw switch in the second mode configured to couple the receive chain to second port, 
 the transmit chain being electrically isolated from the receive chain in the first and second modes. 
 
     
     
       18. The beamforming integrated circuit as defined by  claim 17  wherein the first polarity is substantially orthogonal to the second polarity. 
     
     
       19. The beamforming integrated circuit as defined by  claim 17  wherein the receive chain is electrically connected to neither port in the first mode. 
     
     
       20. The beamforming integrated circuit as defined by  claim 19  wherein the transmit chain is electrically connected to neither port in the second mode. 
     
     
       21. The beamforming integrated circuit as defined by  claim 17  wherein the die substrate comprises a silicon-on-insulator wafer having a device layer and a handle wafer, the handle wafer having a higher resistivity than the device layer, the device layer having the transmit and receive chains. 
     
     
       22. The beamforming integrated circuit as defined by  claim 17  wherein the die substrate includes at least one flip chip interface configured for flip chip bonding.