Low cost apparatus for insitu testing of packaged integrated circuits during stressing

Abstract

An apparatus with a burn-in board containing a microcontroller unit and a heater socket for insitu testing of a packaged integrated circuit while under stress. A method for insitu testing of a packaged integrated circuit while under stress. A method for insitu testing of multiple packaged integrated circuits while under stress.

What is claimed is: 
     
       1. An apparatus comprising:
 a burn-in board; 
 a microcontroller unit (MCU) mounted on the burn-in board; 
 a heater socket defining an open top for receiving a packaged integrated circuit and the heater socket coupled with the MCU; and 
 a heater in the heater socket with the heater positioned to contact a bottom portion of the packaged integrated circuit when the packaged integrated circuit is inserted into the heater socket and over the heater. 
 
     
     
       2. The apparatus of  claim 1 , further comprising a burn-in mother board having a plugin socket configured to receive the burn-in board and wherein the heater socket is mounted on the burn-in board. 
     
     
       3. The apparatus of  claim 2 , wherein the burn-in board is orthogonally arranged with the burn-in mother board. 
     
     
       4. The apparatus of  claim 1 , further comprising:
 a burn-in mother board, wherein the heater socket is mounted on the burn-in mother board; and 
 a plugin socket mounted on the burn-in mother board and configured to receive the burn-in board. 
 
     
     
       5. The apparatus of  claim 1  further comprising an accelerated stress voltage source and the stress voltage source coupled with the MCU. 
     
     
       6. The apparatus of  claim 1  further comprising:
 a first computer configured to program the MCU; and 
 a second computer to implement an accelerated burn-in test. 
 
     
     
       7. The apparatus of  claim 1 , further comprising a computer configured to program the MCU and to implement an accelerated burn-in test. 
     
     
       8. The apparatus of  claim 1  further comprising:
 a first burn-in board and a second burn-in board; 
 a first heater socket and a second heater socket, 
 a first MCU and a second MCU; 
 a burn-in mother board having a first plugin socket configured to receive the first burn-in board and wherein the first heater socket is mounted on the first burn-in board and is coupled to the first MCU, and having a second plugin socket configured to receive the second burn-in board and wherein the second heater socket is mounted on the second burn-in board and is coupled to the second MCU. 
 
     
     
       9. The apparatus of  claim 1 , further comprising:
 a first burn-in board and a second burn-in board; 
 a first heater socket and a second heater socket; 
 a burn-in mother board, wherein the first heater socket and the second heater socket are mounted on the burn-in mother board; 
 a first plugin socket mounted on the burn-in mother board and wherein the first plugin socket is coupled to the first heater socket and wherein the first plugin socket is configured to receive the first burn-in board; and 
 a second plugin socket mounted on the burn-in mother board and wherein the second plugin socket is coupled to the second heater socket and wherein the second plugin socket is configured to receive the second burn-in board. 
 
     
     
       10. A method comprising:
 placing a packaged integrated circuit (IC) over and in contact with a heater mounted to a heater socket mounted on a burn-in board and coupled to a microcontroller unit (MCU) mounted on the burn-in board; 
 receiving an actuation instruction by the MCU to actuate the packaged IC; 
 receiving a stress instruction by the MCU for applying an accelerated stress to the plugged in packaged IC; 
 applying the accelerated stress to the packaged IC based upon the received stress instruction; and 
 collecting test data associated with the accelerated stress. 
 
     
     
       11. The method of  claim 10 , wherein applying the accelerated stress includes applying by the MCU, a voltage greater than an operating voltage of the packaged IC to the packaged IC. 
     
     
       12. The method of  claim 10 , wherein applying the accelerated stress includes applying by the MCU a thermal stress to the packaged IC by activating the heater mounted to the heater socket. 
     
     
       13. The method of  claim 10 , wherein applying the accelerated stress includes applying, by the MCU, a thermal stress by activating the heater mounted to the heater socket, and applying, by the MCU, a voltage greater than an operating voltage of the packaged IC to the packaged IC. 
     
     
       14. The method of  claim 10 , further comprising:
 plugging the burn-in board into a first side of a communication socket inside a burn-in oven; 
 plugging an interface board into a second side of the communication socket outside the burn-in oven; and 
 adjusting the burn-in oven based on a target thermal stressing temperature. 
 
     
     
       15. The method of  claim 10  further comprising:
 transferring the testing data into a memory. 
 
     
     
       16. The method of  claim 10  further comprising:
 determining by the MCU, a failure event of the packaged IC while applying the accelerated stress; 
 recording test data associated with the detected failure event, the test data including at least one of a time of failure, a failed stress condition, or a failed functional test; and 
 transferring the recorded test data into a memory. 
 
     
     
       17. A method comprising:
 placing a first packaged integrated circuit (IC) over and in contact with a first heater mounted to a first heater socket mounted on a first burn-in board and coupled to a first microcontroller unit (MCU) mounted on the first burn-in board; 
 placing a second packaged integrated circuit (IC) over and in contact with a second heater mounted to a second heater socket mounted on a second burn-in board and coupled to a second microcontroller unit (MCU) mounted on the second burn-in board; 
 receiving a first actuation instruction by the first MCU to actuate the first packaged IC; 
 receiving a second actuation instruction by the second MCU to actuate the second packaged IC; 
 receiving a first stress instruction by the first MCU; 
 receiving a second stress instruction by the second MCU; 
 applying an first accelerated stress to the first packaged IC based upon the received first stress instruction; 
 applying an second accelerated stress to the second packaged IC based upon the received second stress instruction; 
 collecting first test data associated with the first accelerated stress; and 
 collecting second test data associated with the second accelerated stress. 
 
     
     
       18. The method of  claim 17 , wherein applying the first accelerated stress includes applying by the first MCU, a first stress voltage greater than a first operating voltage of the first packaged IC to the first packaged IC and wherein applying the second accelerated stress includes applying, by the second MCU, a second stress voltage greater than a second operating voltage of the second packaged IC to the second packaged IC. 
     
     
       19. The method of  claim 18 , wherein the first stress voltage is different than the second stress voltage. 
     
     
       20. The method of  claim 17 , wherein applying the first accelerated stress includes applying, by the first MCU, a first thermal stress to the first packaged IC by activating the first heater mounted to the first heater socket, and wherein applying the second accelerated stress includes applying, by the second MCU, a second thermal stress to the second packaged IC by activating the second heater mounted to the second heater socket. 
     
     
       21. The method of  claim 20 , wherein the first thermal stress is different than the second thermal stress. 
     
     
       22. The method of  claim 17  further comprising:
 detecting a failure event of one or more of the first packaged IC or the second packaged IC; 
 recording test data associated with the failure event, the test data including at least one of a time of failure, a failed stress condition, or a failed functional test; 
 transferring the recorded test data into a memory; 
 removing the accelerated stress from the failed packaged IC; and 
 deactivating the failed packaged IC.