Power-on reset circuit

Abstract

A power-on reset circuit is provided to a semiconductor device including a first power supply pin and N (N≥1) second power supply pins. A voltage monitoring circuit is configured with a voltage at the first power supply pin as its power supply, and compares each of the voltages supplied to the N second power supply pins with a corresponding threshold value. When the supplied voltage exceeds the corresponding threshold value for all the second power supply pins, the voltage monitoring circuit asserts a trigger signal TRIG. A reset signal generating circuit is configured with the voltage at the first power supply pin as its power supply. The reset signal generating circuit asserts a reset signal POR_OUT in response to assertion of the trigger signal TRIG.

What is claimed is: 
     
       1. A power-on reset circuit to be provided to a semiconductor device comprising a first power supply pin and one or more N second power supply pins, the power-on reset circuit comprising:
 a voltage monitoring circuit structured to operate with a voltage at the first power supply pin as a power supply thereof, to compare each from among voltages supplied to the N second power supply pins with a corresponding threshold value, and to assert a trigger signal when the supplied voltage exceeds a corresponding threshold value for all the second power supply pins; and 
 a reset signal generating circuit structured to operate with the voltage at the first power supply pin as a power supply thereof, and to assert a reset signal in response to an assertion of the trigger signal, 
 wherein the voltage monitoring circuit comprises N voltage comparators that correspond to the respective N second power supply pins, and that are each structured to compare a power supply voltage at the corresponding second power supply pin with a corresponding threshold value, 
 wherein N is equal to or greater than 2, 
 wherein the voltage monitoring circuit further comprises a logic circuit structured to generate the trigger signal that corresponds to outputs of the N voltage comparators, 
 wherein the N voltage comparators each comprise an open-drain output stage or otherwise an open-collector output stage, 
 wherein the logic circuit comprises a current source or otherwise an impedance circuit coupled to a common output node of the outputs of the N voltage comparators, and is structured to generate the trigger signal that corresponds to an output of the common output node of the N voltage comparators. 
 
     
     
       2. The power-on reset circuit according to  claim 1 , wherein the reset signal generating circuit comprises a CR (capacitance resistance) time constant circuit. 
     
     
       3. A power-on reset circuit to be provided to a semiconductor device comprising a first power supply pin and one or more N second power supply pins, the power-on reset circuit comprising:
 a voltage monitoring circuit structured to operate with a voltage at the first power supply pin as a power supply thereof, to compare each from among voltages supplied to the N second power supply pins with a corresponding threshold value, and to assert a trigger signal when the supplied voltage exceeds a corresponding threshold value for all the second power supply pins; and 
 a reset signal generating circuit structured to operate with the voltage at the first power supply pin as a power supply thereof, and to assert a reset signal in response to an assertion of the trigger signal, 
 wherein the reset signal generating circuit comprises: 
 a first node; 
 a second node; 
 a first resistor provided between a power supply line coupled to the first power supply pin and the first node; 
 a second resistor provided between the power supply line and the second node; 
 a capacitor provided between the first node and a ground; 
 a first transistor coupled with the capacitor in parallel between the first node and the ground, and structured to receive the trigger signal via a control terminal thereof; 
 a second transistor provided with a third resistor coupled in series between the first node and the ground, and arranged such that a control terminal thereof is coupled to the second node; 
 a third transistor provided between the second node and the ground, and arranged such that a control terminal thereof is coupled to the first node; and 
 an output circuit structured to generate the reset signal that corresponds to a voltage at the first node. 
 
     
     
       4. The power-on reset circuit according to  claim 3 , wherein the output circuit further comprises a Schmitt buffer structured to receive the voltage at the first node. 
     
     
       5. The power-on reset circuit according to  claim 1 , wherein N is equal to or greater than 2,
 wherein the N threshold values that correspond to the N second power supply pins are equal to each other, 
 wherein the power-on reset circuit comprises a fourth resistor and a current source provided in series between a power supply line coupled to the first power supply pin and a ground, 
 and wherein a voltage at a connection node that connects the fourth resistor and the current source is used as the common threshold value. 
 
     
     
       6. The power-on reset circuit according to  claim 5 , wherein the current source comprises an N-channel MOSFET arranged such that a source thereof is grounded and a gate and a drain thereof are coupled. 
     
     
       7. A semiconductor device comprising the power-on reset circuit according to  claim 1 . 
     
     
       8. A semiconductor device comprising:
 a first power supply pin; 
 one or more N second power supply pins; 
 an interface circuit structured to operate receiving a voltage at the first power supply pin; 
 N power-receiving circuits provided corresponding to the N second power supply pins; 
 a power-on reset circuit structured to assert a reset signal when a predetermined voltage is supplied to all the first power supply pin and the N second power supply pins; 
 a first buffer structured to supply the reset signal to the interface circuit; and 
 N second buffers structured to supply the reset signals to the N power-receiving circuits, 
 wherein the power-on reset circuit comprises:
 a voltage monitoring circuit structured to operate with a voltage at the first power supply pin as a power supply thereof, to compare the voltage supplied to each of the N second power supply pins with a corresponding threshold value, and to assert a trigger signal when the supplied voltage exceeds the corresponding threshold value for all the second power supply pins; and 
 a reset signal generating circuit structured to operate with the voltage at the first power supply pin as a power, supply thereof, and to assert a reset signal when an assertion of the trigger signal continues for a predetermined period of time, 
 
 wherein the voltage monitoring circuit comprises N voltage comparators that correspond to the respective N second power supply pins, and that are each structured to compare a power supply voltage at the corresponding second power supply pin with a corresponding threshold value, 
 wherein N is equal to or greater than 2, 
 wherein the voltage monitoring circuit further comprises a logic circuit structured to generate the trigger signal that corresponds to outputs of the N voltage comparators, 
 wherein the N voltage comparators each comprise an open-drain output stage or otherwise an open-collector output stage, and 
 wherein the logic circuit comprises a current source or otherwise an impedance circuit coupled to a common output node of the outputs of the N voltage comparators, and is structured to generate the trigger signal that corresponds to an output of the common output node of the N voltage comparators. 
 
     
     
       9. The semiconductor device according to  claim 8 , further comprising:
 a control pin structured to override the power-on reset circuit; and 
 a test reset pin structured to allow an external reset signal to be received, 
 wherein, when the control pin is set to a predetermined electrical state, a signal that corresponds to the external reset signal is input to the first buffer and the N second buffers instead of inputting the reset signal. 
 
     
     
       10. The semiconductor device according to  claim 8 , wherein the semiconductor device is structured as an audio amplifier circuit,
 wherein the interface circuit comprises a reception circuit structured to receive a digital audio signal from an external processor, 
 wherein one of the N power-receiving circuits comprises a digital signal processing circuit structured to perform signal processing for the digital audio signal, 
 and wherein another one of the N power-receiving circuits comprises a D/A converter structured to convert the digital audio signal subjected to the processing by means of the digital signal processing circuit into an analog audio signal, and an amplifier structured to amplify the analog audio signal. 
 
     
     
       11. The semiconductor device according to  claim 8 , wherein the reset signal generating circuit comprises a CR time constant circuit. 
     
     
       12. The semiconductor device according to  claim 8 , wherein the reset signal generating circuit comprises:
 a first node; 
 a second node; 
 a first resistor provided between a power supply line coupled to the first power supply pin and the first node; 
 a second resistor provided between the power supply line and the second node; 
 a capacitor provided between the first node and a ground; 
 a first transistor coupled with the capacitor in parallel between the first node and the ground, and structured to receive the trigger signal via a control terminal thereof; 
 a second transistor provided with a third resistor coupled in series between the first node and the ground, and arranged such that a control terminal thereof is coupled to the second node; 
 a third transistor provided between the second node and the ground, and arranged such that a control terminal thereof is coupled to the first node; and 
 an output circuit structured to generate the reset signal that corresponds to a voltage at the first node. 
 
     
     
       13. The semiconductor device according to  claim 8 , wherein N is equal to or greater than 2,
 wherein the N threshold values that correspond to the N second power supply pins are equal to each other, 
 wherein the power-on reset circuit comprises a fourth resistor and a current source provided in series between a power supply line coupled to the first power supply pin and a ground, 
 and wherein a voltage at a connection node that connects the fourth resistor and the current source is used as the common threshold value. 
 
     
     
       14. An electronic device comprising:
 the semiconductor device according to  claim 8 ; and 
 a power supply circuit structured to supply a power supply voltage to the first power supply pin and the N second power supply pins of the semiconductor device. 
 
     
     
       15. The power-on reset circuit according to  claim 3 , wherein N is equal to or greater than 2,
 wherein the N threshold values that correspond to the N second power supply pins are equal to each other, 
 wherein the power-on reset circuit comprises a fourth resistor and a current source provided in series between a power supply line coupled to the first power supply pin and a ground, 
 and wherein a voltage at a connection node that connects the fourth resistor and the current source is used as the common threshold value. 
 
     
     
       16. The power-on reset circuit according to  claim 15 , wherein the current source comprises an N-channel MOSFET arranged such that a source thereof is grounded and a gate and a drain thereof are coupled. 
     
     
       17. A semiconductor device comprising the power-on reset circuit according to  claim 3 .