System and method for providing fine-grained memory cacheability during a pre-OS operating environment

Abstract

An information handling system includes a memory with a cache, and a processor to execute pre-operating system (pre-OS) code before the processor executes boot loader code. The pre-OS code sets up a Memory Type Range Register (MTRR) to define a first memory type for a memory region of the memory, sets up a page attribute table (PAT) with an entry to define a second memory type for the memory region, disables the PAT, and pass execution by the processor to the boot loader code. The first memory type specifies a first cacheability setting on the processor for data from the memory region, and the second memory type specifies a second cacheability setting on the processor for data from the memory region.

What is claimed is: 
     
       1. An information handling system, comprising:
 a memory including a cache; and 
 a processor to execute pre-operating system (pre-OS) code before the processor executes boot loader code, the pre-OS code to:
 set up a Memory Type Range Register (MTRR) to define a first memory type for a memory region of the memory, wherein the first memory type specifies a first cacheability setting on the processor for data from the memory region; 
 set up a page attribute table (PAT) with an entry to define a second memory type for the memory region, wherein the second memory type specifies a second cacheability setting on the processor for data from the memory region; 
 disable the PAT; and 
 pass execution by the processor to the boot loader code. 
 
 
     
     
       2. The information handling system of  claim 1 , wherein, after setting up the PAT, but before disabling the PAT, the processor is further to execute the pre-OS code to:
 determine that the pre-OS code includes legacy code to be executed in a 16-bit real mode by the processor. 
 
     
     
       3. The information handling system of  claim 2 , wherein disabling the PAT is in response to determining that the pre-OS code includes the legacy code. 
     
     
       4. The information handling system of  claim 3 , wherein, after disabling the PAT, the processor is further to execute the pre-OS code to:
 run the legacy code, wherein in running the legacy code, the first memory region is accessed by the processor in accordance with the first memory type as specific by the MTRR; and 
 after running the legacy code, re-enable the PAT. 
 
     
     
       5. The information handling system of  claim 4 , wherein, after re-enabling the PAT, the processor is further to execute the pre-OS code to:
 access a memory mapped input/output (MMIO) device at the first memory region in accordance with the second memory type as specified by the PAT entry. 
 
     
     
       6. The information handling system of  claim 1 , wherein the first cacheability setting specifies that data from the memory region is uncacheable and the second cacheability setting specifies that data from the memory region is cacheable. 
     
     
       7. The information handling system of  claim 6 , wherein, prior to disabling the PAT, the processor is further to execute the pre-OS code to:
 access a memory mapped input/output (MMIO) device at the first memory region in accordance with the second memory type as specified by the PAT entry; and 
 store data retrieved from the memory region in the cache. 
 
     
     
       8. The information handling system of  claim 7 , wherein the MMIO device comprises a flash memory device and the second cacheability setting provides that the first memory region is write protected. 
     
     
       9. The information handling system of  claim 7 , wherein the MMIO device comprises a video frame buffer and the second cacheability setting provides that the first memory region is write combined. 
     
     
       10. A method, comprising:
 setting up, by a pre-operating system (pre-OS) code executable by a processor of an information handling system before the processor executes boot loader code, a Memory Type Range Register (MTRR) of the processor to define a first memory type for a memory region of a memory of the information handling system before the processor executes boot loader code, wherein the processor includes a cache, and wherein the first memory type specifies a first cacheability setting on the processor for data from the memory region; 
 setting up, by the pre-OS code, a page attribute table (PAT) with an entry to define a second memory type for the memory region, wherein the second memory type specifies a second cacheability setting on the processor for data from the memory region; 
 disabling, by the pre-OS code, the PAT; and 
 passing, by the pre-OS code, execution by the processor to the boot loader code. 
 
     
     
       11. The method of  claim 10 , wherein, after setting up the PAT, but before disabling the PAT, the method further comprises:
 determining that the pre-OS code includes legacy code to be executed in a 16-bit real mode by the processor. 
 
     
     
       12. The method of  claim 11 , wherein disabling the PAT is in response to determining that the pre-OS code includes the legacy code. 
     
     
       13. The method of  claim 12 , wherein, after disabling the PAT, the method further comprises:
 running the legacy code, wherein in running the legacy code, the first memory region is accessed by the processor in accordance with the first memory type as specific by the MTRR; and 
 after running the legacy code, re-enabling the PAT. 
 
     
     
       14. The method of  claim 13 , wherein, after re-enabling the PAT, the method further comprises:
 accessing a memory mapped input/output (MMIO) device at the first memory region in accordance with the second memory type as specified by the PAT entry. 
 
     
     
       15. The method of  claim 10 , wherein the first cacheability setting specifies that data from the memory region is uncacheable and the second cacheability setting specifies that data from the memory region is cacheable. 
     
     
       16. The method of  claim 15 , wherein, prior to disabling the PAT, the method further comprises:
 accessing a memory mapped input/output (MMIO) device at the first memory region in accordance with the second memory type as specified by the PAT entry; and 
 storing data retrieved from the memory region in the cache. 
 
     
     
       17. The method of  claim 16 , wherein the MMIO device comprises a flash memory device and the second cacheability setting provides that the first memory region is write protected. 
     
     
       18. The method of  claim 16 , wherein the MMIO device comprises a video frame buffer and the second cacheability setting provides that the first memory region is write combined. 
     
     
       19. A method, comprising:
 setting up, by a pre-operating system (pre-OS) code executable by a processor of an information handling system before the processor executes boot loader code, a page attribute table (PAT) with an entry to define a memory type for a memory region of a memory of the information handling system before the processor executes boot loader code, wherein the memory type specifies a cacheability setting on the processor for data from the memory region; 
 determining that the pre-OS code includes legacy code to be executed in a 16-bit real mode by the processor; 
 disabling, by the pre-OS code, the PAT in response to determining that the pre-OS code includes legacy code; 
 running the legacy code, wherein in running the legacy code, the memory region is accessed by the processor in accordance with the second memory type as specific by an MTRR of the processor; 
 re-enabling, by the pre-OS code, the PAT after running the legacy code; and 
 disabling, by the pre-OS code, the PAT prior to passing execution by the processor to the boot loader code. 
 
     
     
       20. The method of  claim 19 , wherein the cacheability setting specifies that data from the memory region is cacheable.