Multi-mode memory module with data handlers

Abstract

A memory subsystem is operable with a system memory controller. The memory subsystem comprises memory devices mounted on a circuit board, a data module mounted on the circuit board; and a control module mounted on the circuit board to provide address and control signals to the memory devices. The memory subsystem is operable in any of a plurality of modes including a normal mode and a test mode. During the normal mode, the control module provides the address and control signals based on address and control signals from the system memory controller, and the data module enables data paths between the memory devices and the system memory controller. During the test mode, the control module generates the address and control signals, and the data module isolates the memory devices from the system memory controller.

What is claimed is: 
     
       1. A memory module accessible in a computer system by a system memory controller via a system memory bus, comprising:
 memory devices mounted on a circuit board, the memory devices having address and control ports and data ports; 
 a data module mounted on the circuit board and coupled between the data ports of the memory devices and the system memory bus, the data module including data handler logic elements; and 
 a control module mounted on the circuit board and coupled to the data module, the address and control ports of the memory devices, and the system memory bus; and 
 wherein the memory module is operable in any of a plurality of modes including a first mode and a second mode; 
 wherein the control module in the first mode is configured to receive system address and control signals from the system memory controller and to output first memory address and control signals to the memory devices according to the system address and control signals, and the data module in the first mode is configured to propagate one or more first data signals between the memory devices and the system memory controller, the one or more first data signals being transmitted or received by at least a portion of the memory devices in response to the first memory address and control signals; and 
 wherein the control module in the second mode is configured to output second memory address and control signals to the address and control ports of the memory devices, and the data module in the second mode is configured to isolate the memory devices from being accessed by the system memory controller and to transmit one or more second data signals including data patterns provided by the data handler logic elements to the data ports of the memory devices according to one or more commands output from the control module, and wherein at least a portion of the memory devices are configured to receive the one or more second data signals according to the second memory address and control signals from the control module. 
 
     
     
       2. The memory module of  claim 1 , wherein the memory devices are arranged in at least one rank and organized in a plurality of memory device groups, each rank of the at least one rank having a set of memory devices across a full bit width of the memory module, each respective memory device group of the plurality of memory device groups including respective one or more memory devices in each rank of the at least one rank, wherein each data signal of the one or more first data signals propagated by the data module during the first mode is N-bits wide, wherein the data module includes a plurality of data handlers, each respective data handler of the plurality of data handlers including a respective one of the data handler logic elements, wherein the each respective data handler is configured to propagate a respective n-bit section of the each data signal of the one or more first data signals between the system memory controller and a respective memory device group of the plurality of memory device groups, n being a fraction of N, and wherein the each respective data handler is further configured to output a respective n-bit wide section of each of the one or more second data signals including one or more respective n-bit-wide data patterns provided by the respective one of the data handler logic elements to the respective memory device group. 
     
     
       3. The memory module of  claim 2 , wherein each memory device is n-bits wide and wherein the respective memory device group includes a single respective memory device in each rank of the at least one rank. 
     
     
       4. The memory module of  claim 2 , wherein the control module is configured to output third memory address and control signals to the address and control ports of the memory devices during the second mode, the third memory address and control signals causing the memory devices in one of the at least one rank to output at least one N-bit wide read data signal, and wherein the each respective data handler is configured to receive a respective n-bit section of each of the at least one N-bit wide read data signal. 
     
     
       5. The memory module of  claim 4 , wherein the each respective data handler is configured to check the respective n-bit section of each of the at least one N-bit wide read data signal with respect to a corresponding data pattern stored in the respective data handler logic element. 
     
     
       6. The memory module of  claim 5 , wherein the data module is configured to store failure information when a test failure is indicated by the respective n-bit section of each of the at least one N-bit wide read data signal not being in agreement with the corresponding data pattern. 
     
     
       7. The memory module of  claim 6 , wherein the data module is further configured to report the failure information to the control module. 
     
     
       8. The memory module of  claim 2 , wherein the plurality of data handlers are configured to operate independently of each other without being in communication with each other. 
     
     
       9. The memory module of  claim 2 , wherein the plurality of data handlers include physically separate integrated circuit packages, and wherein the each respective data handler is disposed on the circuit board at a position corresponding to the respective memory device group. 
     
     
       10. The memory module of  claim 2 , wherein the each respective data handler includes first data paths between the respective memory device group and the system memory controller and second data paths between the respective memory device group and the respective one of the data handler logic elements, and wherein the each respective data handler is configured to propagate the respective n-bit section of the each data signal of the one or more first data signals using the first data paths, and is further configured to transmit the respective n-bit wide section of each of the one or more second data signals using the second data paths. 
     
     
       11. The memory module of  claim 10 , wherein the each respective data handler is further configured to isolate the first data paths in the second mode. 
     
     
       12. The memory module of  claim 2 , wherein each memory device is n/2-bit wide and wherein the respective memory device group includes two respective memory devices in each of the at least one rank. 
     
     
       13. The memory module of  claim 2 , wherein the second data signals are received by a selected rank of the one or more ranks according to the second memory address and control signals from the control module. 
     
     
       14. The memory module of  claim 2 , wherein the respective n-bit-wide data pattern is based on information which the respective one of the data handler logic elements receives from the control module. 
     
     
       15. The memory module of  claim 1 , wherein the data module is configured to output the one or more second data signals to the memory devices in response to a write command output from the control module, and wherein the data module is further configured to receive the at least one N-bit wide read data signal from the memory devices in response to a read command output from the control module. 
     
     
       16. The memory module of  claim 1 , wherein the memory devices are arranged in one or more ranks, each rank of the one or more ranks having a set of memory devices across a full bit width of the memory module, and wherein the second data signals are received by a selected rank of the one or more ranks according to the second memory address and control signals from the control module. 
     
     
       17. The memory module of  claim 1 , wherein the data patterns provided by the data handler logic elements are based on information that the data handler logic elements receive from the control module. 
     
     
       18. The memory module of  claim 1 , wherein the control module is further configured to provide the data patterns to the data module. 
     
     
       19. A memory module operable in a computer system with a system memory controller, the memory module comprising:
 a printed circuit board (PCB) having a connector configured to provide electrical connections for data, address and control signals between the memory module and the system memory controller; 
 memory devices mounted on the PCB and arranged in one or more ranks, each respective rank of the one or more ranks having a respective set of memory devices across a full bit-width of the memory module; 
 a control module mounted on the PCB and electrically coupled to the connector and to the memory devices, wherein the control module is configured to output address and control signals to the memory devices based on information received via the connector; and 
 a plurality of data handlers mounted on the PCB, wherein each respective data handler of the plurality of data handlers includes a data handler logic element, wherein each respective data handler of the plurality of data handlers is electrically coupled between a respective group of one or more memory devices and the connector, the respective group of one or more memory devices including at least one respective memory device in each of the one or more ranks; 
 wherein the memory module is configurable to operate in any of at least a first mode and a second mode; 
 wherein, in the first mode, the memory module is configured to be accessed by the system memory controller for memory read and write operations, and the data handlers are configured to propagate one or more data signals associated with the memory read or write operations between the memory devices and the connector; 
 wherein, in the second mode, the memory devices are not accessed by the system memory controller, and the data handler logic element in the each respective data handler is configured to provide respective data patterns to the respective group of one or more memory devices based on information output from the control module. 
 
     
     
       20. The memory module of  claim 19 , wherein each of the one or more data signals is N-bit wide, and wherein, when the memory module is operating in the first mode, the each respective data handler is configured to propagate a respective n-bit section of each of the one or more data signals between at least one respective memory device in the at least one rank and the connector, n being a fraction of N; and wherein, when the memory module is operating in the second mode, the respective data patterns are each n-bits wide. 
     
     
       21. The memory module of  claim 20 , wherein each memory device is n-bit wide and wherein the respective group of one or more memory devices include a single respective memory device in each of the one or more ranks. 
     
     
       22. The memory module of  claim 20 , wherein each memory device is n/2-bit wide and wherein the respective group of one or more memory devices include two respective memory devices in each of the one or more ranks. 
     
     
       23. The memory module of  claim 20 , wherein the each respective data handler includes first data paths between the respective group of one or more memory devices and the connector, and further includes second data paths between the respective group of one or more memory devices and the respective data handler logic element, and wherein the each respective data handler is configured to propagate the respective n-bit section of the each of the one or more data signals using the first data paths, and is further configured to provide the respective data patterns using the second data paths. 
     
     
       24. The memory module of  claim 20 , wherein, in the second mode, the each respective data handler is further configured to isolate the respective group of one or more memory devices from the connector. 
     
     
       25. The memory module of  claim 20 , wherein the respective group of one or more memory devices are configured to receive or output the respective n-bit section of each of the one or more data signals in response to corresponding address and control signals output from the control module. 
     
     
       26. The memory module of  claim 20 , wherein the each respective data handler is configured to output the respective data patterns to the respective group of one or more memory devices in response to a write command output from the control module. 
     
     
       27. The memory module of  claim 20 , wherein the respective group of one or more memory devices are configured to receive the respective data patterns in response to corresponding address and control signals output from the control module. 
     
     
       28. The memory module of  claim 19 , wherein the plurality of data handlers include physically separate integrated circuit packages, and wherein the each respective data handler is disposed on the circuit board at a position corresponding to the respective group of one or more memory devices. 
     
     
       29. The memory module of  claim 19 , wherein the each respective data handler is configured to output the respective data patterns to the respective group of one or more memory devices in response to one or more write commands output from the control module. 
     
     
       30. The memory module of  claim 29 , wherein, when the memory module is operating in the second mode, the each respective data handler is further configured to receive read data patterns from the respective group of one or more memory devices in response to one or more read commands output from the control module. 
     
     
       31. The memory module of  claim 30 , wherein the each respective data handler is further configured to check the read data patterns received from the respective group of one or more memory devices with respect to corresponding data patterns stored in the each respective data handler. 
     
     
       32. The memory module of  claim 19 , wherein, in the second mode, the each respective data handler is further configured to isolate the respective group of one or more memory devices from the connector. 
     
     
       33. The memory module of  claim 19 , wherein the memory devices are configured to receive or output the one or more data signals in response to corresponding address and control signals output from the control module. 
     
     
       34. The memory module of  claim 19 , wherein the memory devices are configured to receive the data patterns provided by the data handlers in response to corresponding address and control signals output form the control module.