Semiconductor device having dummy active fin patterns

Abstract

A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a circuit region and a dummy region adjacent to each other; 
 circuit active fin patterns in the circuit region and having a linear shape extended in a first direction; 
 dummy active fin patterns in the dummy region and having a linear shape extended in the first direction, the dummy active fin patterns including first-side fin patterns having end portions opposing end portions of the circuit active fin patterns; 
 circuit gate lines in the circuit region and intersecting the circuit active fin patterns; and 
 dummy gate lines in the dummy region and having end portions opposing end portions of the circuit gate lines, 
 wherein sides of the circuit active fin patterns and sides of the first-side fin patterns are aligned with each other, and 
 wherein sides of the circuit gate lines and sides of the dummy gate lines are aligned with each other. 
 
     
     
       2. The semiconductor device as claimed in  claim 1 , wherein:
 the dummy region includes a first dummy region and a second dummy region located in the second direction of the circuit region, 
 the circuit region includes a first circuit region opposing the first dummy region and a second circuit region spaced apart from the first dummy region, 
 the first dummy region is between the second dummy region and the first circuit region, and 
 the dummy active fin patterns includes second-side fin patterns disposed in the first and second dummy regions. 
 
     
     
       3. The semiconductor device as claimed in  claim 2 , further comprising:
 a circuit active region within the first circuit region; 
 a first dummy active region in the first dummy region; and 
 a second dummy active region in the second dummy region, 
 wherein the circuit active fin patterns are on the circuit active region, and 
 wherein the second-side fin patterns of the dummy active fin patterns are on the first and second dummy active regions. 
 
     
     
       4. The semiconductor device as claimed in  claim 3 , wherein the circuit active region has a width different from a width of the first dummy active region, and the second dummy active region has a width different from a width of the first dummy active region. 
     
     
       5. The semiconductor device as claimed in  claim 4 , wherein the first dummy active region includes portions having different widths, of which the number of the dummy active fin patterns disposed on a portion having a relatively great width, among the portions having different widths, is higher than the number of the dummy active fin patterns on a portion having a relatively narrow width. 
     
     
       6. A semiconductor device, comprising:
 circuit active fin lines and circuit gate lines intersecting each other in a circuit active region; 
 dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the circuit active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, 
 wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines. 
 
     
     
       7. The semiconductor device as claimed in  claim 6 , wherein the at least some of the dummy active fin lines have end portions opposing end portions of the circuit active fin lines, and the at least some of the dummy gate lines have end portions opposing end portions of the circuit gate fin lines. 
     
     
       8. The semiconductor device as claimed in  claim 7 , wherein the at least some of the dummy active fin lines are disposed on virtual linear lines extended from the circuit active fin lines, and at least of the dummy gate fin lines are disposed on virtual linear lines extended from the circuit gate lines. 
     
     
       9. The semiconductor device as claimed in  claim 6 , further comprising a first space between some of the circuit active fin lines and dummy active fin lines, and a second space between some of the circuit gate lines and the dummy gate lines. 
     
     
       10. The semiconductor device as claimed in  claim 6 , wherein a density of the dummy active fin lines in the dummy active region is different from a density of the circuit active fin lines in the circuit active region.