Semiconductor device

Abstract

A semiconductor device according to an embodiment includes a semiconductor substrate having a first plane and a second plane, a plurality of first semiconductor areas provided on the first plane, a plurality of second semiconductor areas provided between the plurality of first semiconductor areas, a plurality of insulator regions provided between the first semiconductor areas and the second semiconductor areas, first-conductivity-type drain regions provided in the first semiconductor areas, first-conductivity-type source regions provided in the second semiconductor areas, gate electrodes, first-conductivity-type first impurity regions that are provided between the first-conductivity-type drain regions and the second plane and have a lower first-conductivity-type impurity concentration than the first-conductivity-type drain regions, and a plurality of second-conductivity-type second impurity regions provided between the first-conductivity-type source regions and the second plane. The width of at least one of the plurality of first semiconductor areas is greater than the width of the other first semiconductor areas.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a semiconductor substrate having a first plane and a second plane; 
 a plurality of insulator regions provided in the semiconductor substrate on a first plane side of the semiconductor substrate; 
 a plurality of first semiconductor areas provided on the first plane, the first semiconductor areas extending in a first direction, each of the plurality of first semiconductor areas being interposed between two of the plurality of insulator regions; 
 a plurality of second semiconductor areas provided on the first plane, the plurality of second semiconductor areas extending in the first direction, the plurality of second semiconductor areas being provided between the plurality of first semiconductor areas; 
 a plurality of first-conductivity-type drain regions provided in the plurality of first semiconductor areas; 
 a plurality of first-conductivity-type source regions provided in the plurality of second semiconductor areas; 
 a plurality of gate electrodes provided between the plurality of first-conductivity-type drain regions and the plurality of first-conductivity-type source regions, the plurality of gate electrodes provided above the plurality of second semiconductor areas and the plurality of insulator regions; 
 a plurality of first-conductivity-type first impurity regions provided between the plurality of first-conductivity-type drain regions and the second plane, the plurality of first-conductivity-type first impurity regions having a lower first-conductivity-type impurity concentration than the plurality of first-conductivity-type drain regions; and 
 a plurality of second-conductivity-type second impurity regions provided between the plurality of first-conductivity-type source regions and the second plane, 
 wherein a width of at least one first semiconductor area among the plurality of first semiconductor areas is greater than a width of the other first semiconductor areas, 
 wherein the two of the plurality of insulator regions interposing each of the plurality of first semiconductor areas are provided in a same one of the plurality of first-conductivity-type first impurity regions. 
 
     
     
       2. The semiconductor device according to  claim 1 ,
 wherein the at least one first semiconductor area among the plurality of first semiconductor areas is located at an end of the plurality of first semiconductor areas. 
 
     
     
       3. The semiconductor device according to  claim 1 ,
 wherein the width of the at least one first semiconductor area is equal to or greater than two times the width of the other first semiconductor areas. 
 
     
     
       4. The semiconductor device according to  claim 1 ,
 wherein the width of the at least one first semiconductor area is equal to or greater than 1.2 μm. 
 
     
     
       5. The semiconductor device according to  claim 1 ,
 wherein the width of the other first semiconductor areas is equal to or less than 0.5 μm. 
 
     
     
       6. The semiconductor device according to  claim 1 , further comprising:
 a second-conductivity-type third impurity region provided between the first-conductivity-type first impurity region and the second plane, the second-conductivity-type third impurity region having a lower second-conductivity-type impurity concentration than the second-conductivity-type second impurity region; 
 a first-conductivity-type fourth impurity region provided between the first-conductivity-type first impurity region and the second-conductivity-type third impurity region, the first-conductivity-type fourth impurity region having a higher first-conductivity-type impurity concentration than the first-conductivity-type first impurity region; and 
 a second-conductivity-type fifth impurity region provided between the first-conductivity-type first impurity region and the first-conductivity-type fourth impurity region, the second-conductivity-type fifth impurity region having a lower second-conductivity-type impurity concentration than the second-conductivity-type second impurity region. 
 
     
     
       7. The semiconductor device according to  claim 6 ,
 wherein the first-conductivity-type fourth impurity region includes antimony (Sb). 
 
     
     
       8. The semiconductor device according to  claim 6 ,
 wherein the first-conductivity-type impurity concentration of the first-conductivity-type fourth impurity region is equal to or greater than 1×10 20  cm −3  and equal to or less than 1×10 22  cm −3 . 
 
     
     
       9. The semiconductor device according to  claim 1 ,
 wherein the semiconductor substrate is made of silicon. 
 
     
     
       10. The semiconductor device according to  claim 1 ,
 wherein the first conductivity type is an n type and the second conductivity type is a p type.