Signal processing device and associate equalization circuit and signal processing method

Abstract

A signal processing device for a receiver includes: a descrambler, descrambling an input signal to generate a descrambled signal; a phase recovery circuit, performing phase recovery according to the descrambled signal to generate a phase recovered signal; an equalization module, performing equalization according to the phase recovered signal to generate an equalized signal; and a decoder, decoding the equalized signal to obtain data included in the input signal.

What is claimed is: 
     
       1. A signal processing device for a receiver, comprising:
 a descrambler, descrambling an input signal to generate a descrambled signal; 
 a phase recovery circuit, performing phase recovery according to the descrambled signal to generate a phase recovered signal; 
 an equalization module, performing equalization according to the phase recovered signal to generate an equalized signal; and 
 a decoder, decoding the equalized signal to obtain data included in the input signal, 
 wherein the equalization module comprises: 
 a first scrambler, scrambling the phase recovered signal to generate a scrambled phase recovered signal; 
 an equalization circuit, performing the equalization according to the scrambled phase recovered signal to generate a scrambled equalized signal; and 
 a first descrambler, descrambling the scrambled equalized signal to generate the equalized signal. 
 
     
     
       2. The signal processing device according to  claim 1 , further comprising:
 a frontend circuit, converting a radio-frequency signal to a baseband signal; 
 a timing recovery circuit, performing timing recovery on the baseband signal to generate a timing recovered signal; and 
 a frame synchronization circuit, performing frame synchronization according to the timing recovered signal to generate a frame synchronized signal; 
 wherein, the descrambler is coupled between the frame synchronization circuit and the phase recovery circuit, and the input signal is the frame synchronized signal. 
 
     
     
       3. The signal processing device according to  claim 1 , wherein the equalization circuit comprises:
 a feedforward estimation circuit, performing feedforward estimation according to the scrambled phase recovered signal and a slicing error signal to generate the scrambled equalized signal; 
 a second descrambler, descrambling the scrambled equalized signal to generate another equalized signal; 
 a decision-directed slicer, slicing the another equalized signal to generate a sliced signal; 
 a second scrambler, scrambling the sliced signal to generate a scrambled sliced signal; and 
 an arithmetic circuit, generating the slicing error signal to the feedforward estimation circuit according to the scrambled sliced signal and the scrambled equalized signal. 
 
     
     
       4. A signal processing method for a receiver, comprising:
 descrambling an input signal to generate a descrambled signal; 
 performing phase recovery according to the descrambled signal to generate a phase recovered signal; 
 performing equalization according to the phase recovered signal to generate an equalized signal; and 
 decoding the equalized signal to obtain data included in the input signal, 
 wherein the step of performing the equalization according to the phase recovered signal to generate the equalized signal comprises: 
 scrambling the phase recovered signal to generate a scrambled phase recovered signal; 
 performing the equalization according to the scrambled phase recovered signal to generate a scrambled equalized signal; and 
 descrambling the scrambled equalized signal to generate the equalized signal. 
 
     
     
       5. The signal processing method according to  claim 4 , further comprising:
 converting a radio-frequency signal to a baseband signal; 
 performing timing recovery on the baseband signal to generate a timing recovered signal; and 
 performing frame synchronization according to the timing recovered signal to generate a frame synchronized signal; 
 wherein, the input signal is the frame synchronized signal. 
 
     
     
       6. The signal processing method according to  claim 5 , wherein the step of performing the equalization signal according to the scrambled phase recovered signal to generate the scrambled equalized signal comprises:
 performing feedforward estimation according to the scrambled phase recovered signal and a slicing error signal to generate the scrambled equalized signal; 
 descrambling the scrambled equalized signal to generate another equalized signal; 
 slicing the another equalized signal to generate a sliced signal; 
 scrambling the sliced signal to generate a scrambled sliced signal; and 
 generating the slicing error signal according to the scrambled sliced signal and the scrambled equalized signal. 
 
     
     
       7. A signal processing device for a receiver, comprising:
 a first scrambler, scrambling a phase recovered signal, generated by performing phase recovery according to descrambled signal derived from an input signal, to generate a scrambled phase recovered signal; 
 an equalization circuit, performing equalization according to the scrambled phase recovered signal to generate a scrambled equalized signal; and 
 a first descrambler, descrambling the scrambled equalized signal to generate an equalized signal, which is provided to a decoder that decodes the equalized signal to obtain data included in the input signal. 
 
     
     
       8. The signal processing device for a receiver of  claim 7 , wherein the equalization circuit comprises:
 a feedforward estimation circuit, performing feedforward estimation according to the scrambled phase recovered signal and a slicing error signal to generate the scrambled equalized signal; 
 a second descrambler, descrambling the scrambled equalized signal to generate another equalized signal; 
 a decision-directed slicer, slicing the another equalized signal to generate a sliced signal; 
 a second scrambler, scrambling the sliced signal to generate a scrambled sliced signal; and 
 an arithmetic circuit, generating the slicing error signal to the feedforward estimation circuit according to the scrambled sliced signal and the scrambled equalized signal.