Method and apparatus to reduce effect of dielectric absorption in SAR ADC

Abstract

A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.

The invention claimed is: 
     
       1. An analog to digital converter (ADC) comprising:
 a converter circuit configured to produce a first digital conversion output signal value based upon a first analog signal input to the ADC and to produce a second digital conversion output signal value based upon a second analog signal input to the ADC selected subsequent to selection of the first analog signal; and 
 a correction circuit configured to:
 receive the first and second digital conversion output signal values; 
 receive at least one of an acquisition time signal or a temperature signal, the acquisition time signal representing a duration of time between two adjacent analog to digital conversions; and 
 determine a corrected version of the second digital conversion output value using information about the first digital conversion output value and the received at least one of the acquisition time signal or temperature signal. 
 
 
     
     
       2. The converter of  claim 1 , wherein the first digital conversion output value includes a corrected version of the first digital conversion value. 
     
     
       3. The converter of  claim 1 ,
 wherein the correction circuit is configured to: 
 determine a scaling factor value based at least in part upon the analog signal acquisition time and the temperature of the converter circuit; 
 determine a first difference value between the first digital conversion output value and the second digital conversion output value and 
 determine a product of the scaling factor value and the first difference value. 
 
     
     
       4. The converter of  claim 1 ,
 wherein the correction circuit is configured to: 
 determine a scaling factor value based at least in part upon the analog signal acquisition time and the temperature; 
 determine a first difference value between the first digital conversion output value and the corrected first digital conversion output and the second digital conversion output value; 
 determine a product of the scaling factor value and the first difference value; and 
 determine a sum of the determined product and the second digital conversion output value. 
 
     
     
       5. The converter of  claim 4 ,
 wherein the correction circuit includes a look up table that stores the determined scaling factor value; 
 wherein the correction circuit includes subtraction circuit to determine the first difference value; 
 wherein the correction circuit includes a multiplication circuit to determine the product; and 
 wherein the correction circuit includes an adder circuit to determine the sum. 
 
     
     
       6. The converter of  claim 1 ,
 wherein the correction circuit is configured to: 
 determine a scaling factor value based at least in part upon the analog signal acquisition time and the temperature; and 
 determine a product of the scaling factor value and the second digital conversion output value. 
 
     
     
       7. The converter of  claim 1 ,
 wherein the correction circuit is configured to: 
 determine a scaling factor value based at least in part upon the analog signal acquisition time and the temperature; 
 determine a product of the scaling factor value and a previous analog signal value; and 
 determine a difference between the determined product and the second digital conversion output value. 
 
     
     
       8. The converter of  claim 1 ,
 wherein the correction circuit includes a look up table in a computer readable storage device; 
 wherein the correction circuit is configured to determine a scaling factor based on the analog signal acquisition time and the temperature, and 
 wherein the computer readable storage device stores the determined scaling factor value. 
 
     
     
       9. The converter of  claim 7 ,
 wherein the correction circuit includes a look up table that stores the determined scaling factor value; 
 wherein the correction circuit includes a multiplication circuit to determine the product value; and 
 wherein the correction circuit includes a subtraction circuit to determine the difference value. 
 
     
     
       10. The converter of  claim 1 , wherein the duration is computed based on a difference between a first time point identifying when a first conversion cycle ends and a second time point identifying when an adjacent second conversion cycle starts. 
     
     
       11. A method to reduce dielectric absorption in an analog to digital converter (ADC), the method comprising:
 producing a first digital conversion output signal value in response to a first analog input to the ADC; 
 producing a second digital conversion output signal value in response to a second analog input to the ADC selected subsequent to selection of the first analog input; 
 receiving at least one of an acquisition time signal or a temperature signal, the acquisition time signal representing a duration of time between two adjacent analog to digital conversions; 
 determining a scaled first digital conversion output value based at least in part upon the received at least one of the acquisition time signal or the temperature signal; and 
 adjusting the second digital conversion output signal value based at least in part upon the determined scaled first digital conversion output value. 
 
     
     
       12. The method of  claim 11 , wherein the first digital conversion output value includes a corrected first digital conversion value. 
     
     
       13. The method of  claim 11 , further comprising determining the duration based on a start of a present conversion cycle and a time of completion of an adjacent preceding conversion cycle. 
     
     
       14. The method of  claim 11 , wherein the duration is computed based on a difference between a first time point identifying when a first conversion cycle ends and a second time point identifying when an adjacent second conversion cycle starts, further comprising:
 coupling a capacitor array to receive the first analog input and in response providing the first digital conversion output value based on the first analog input; and 
 after providing the first digital conversion output value, coupling the capacitor array to receive the second analog input and in response providing the second digital conversion output value based on the second analog input. 
 
     
     
       15. The converter of  claim 1 , wherein the correction circuit is further configured to:
 determine a scaled version of the first digital conversion output value using the received at least one of the acquisition time signal or temperature signal; and 
 determine the corrected version of the second digital conversion output value using the scaled version of the first digital conversion output value and the received at least one of the acquisition time signal or temperature signal. 
 
     
     
       16. The converter of  claim 1 , wherein the correction circuit is configured to determine the corrected version of the second digital conversion output value using the information about the first digital conversion output value, and the acquisition time and temperature signals. 
     
     
       17. The converter of  claim 1 , wherein the duration is determined based on a start of a present conversion cycle and a time of completion of an adjacent preceding conversion cycle. 
     
     
       18. The converter of  claim 1 , wherein the correction circuit is configured to receive the acquisition time signal and use the acquisition time signal to determine the corrected version. 
     
     
       19. The converter of  claim 1 , wherein the correction circuit is configured to receive the temperature signal and use the temperature signal to determine the corrected version. 
     
     
       20. The method of  claim 11 , wherein the acquisition time signal is received and used to determine the scaled first digital conversion output value. 
     
     
       21. The method of  claim 11 , wherein the temperature signal is received and used to determine the scaled first digital conversion output value. 
     
     
       22. An apparatus comprising:
 means for producing a first digital conversion output signal value in response to a first analog input to an analog to digital converter (ADC); 
 means for producing a second digital conversion output signal value in response to a second analog input to the ADC selected subsequent to selection of the first analog input; 
 means for receiving at least one of an acquisition time signal or a temperature signal, the acquisition time signal representing a duration of time between two adjacent analog to digital conversions; 
 means for producing a corrected version of the first digital conversion output value based at least in part upon the received at least one of the acquisition time signal or the temperature signal; and 
 means for producing a corrected version of the second digital conversion output signal value based at least in part upon the corrected version of the first digital conversion output value. 
 
     
     
       23. The apparatus of  claim 22 , wherein the acquisition time signal is received and used to determine the scaled first digital conversion output value. 
     
     
       24. The apparatus of  claim 22 , wherein the temperature signal is received and used to determine the scaled first digital conversion output value. 
     
     
       25. The apparatus of  claim 22 , further comprising means for determining the duration based on a start of a present conversion cycle and a time of completion of an adjacent preceding conversion cycle. 
     
     
       26. The apparatus of  claim 22 , wherein the duration is computed based on a difference between a first time point identifying when a first conversion cycle ends and a second time point identifying when an adjacent second conversion cycle starts, further comprising:
 means for coupling a capacitor array to receive the first analog input and in response providing the first digital conversion output value based on the first analog input; and 
 means for after providing the first digital conversion output value, coupling the capacitor array to receive the second analog input and in response providing the second digital conversion output value based on the second analog input.