Dual reset branch analog-to-digital conversion

Abstract

Methods and systems for analog-to-digital conversion using two side branches that may be operated with overlapped timing such that a sampling phase may be overlapped with a previous conversion phase. Some embodiments provide a method of successive approximation A/D converting, comprising sampling a first signal onto a first capacitor that is configured to selectively couple to an analog input of a comparator, sampling a second signal onto capacitors that are coupled to a second analog input of the comparator and configured for charge redistribution successive approximation A/D conversion; carrying out, based on the first signal and the second signal, a charge redistribution successive approximation A/D conversion using the capacitors; and while carrying out the charge redistribution successive approximation A/D conversion based on the first and second signals, sampling a third signal onto a third capacitor that is configured to selectively couple to the analog input of a comparator.

What is claimed is: 
     
       1. An analog-to-digital converter (ADC), comprising:
 a comparator having a first input and a second input; 
 a first-side branch that comprises a binary-weighted capacitor array and that is configured to sample a voltage signal onto the binary-weighted capacitor array, wherein an output from the binary-weighted capacitor array is coupled to the first input of the comparator; 
 a plurality of second-side branches, each second-side branch configured to sample a respective voltage and having a respective output; and wherein the SAR ADC is configured to selectively couple each of the outputs of the second-side branches separately to the second input of the comparator; and 
 control logic that is operable to cause:
 sampling a first signal by a first one of the plurality of second-side branches; 
 sampling a second signal onto the binary-weighted capacitor array; 
 carrying out, based on the first signal and the second signal, a charge redistribution successive approximation A/D conversion using the binary-weighted capacitor array; and 
 while carrying out the charge redistribution successive approximation A/D conversion based on the first and second signals, sampling a third signal onto a second one of the plurality of side branches; 
 
 wherein the third signal is to be used with a fourth signal sampled onto the binary-weighted capacitor array after carrying out the charge redistribution successive approximation A/D conversion, for carrying out a subsequent charge redistribution successive approximation A/D conversion using the binary-weighted capacitor array based on the third and fourth signals. 
 
     
     
       2. The ADC according to  claim 1 , wherein the plurality of second-side branches are implemented as not more than two second-side branches, the number of second-side branches thereby being two. 
     
     
       3. The ADC according to  claim 1 , further comprising a series of more than two voltage references configured for selective coupling to the binary-weighted capacitor array for selecting two of the voltage references for use in successive approximation control of the binary-weighted capacitor array and in establishing at least one most-significant bit during operation of the ADC. 
     
     
       4. An image sensor, comprising:
 an array of pixels; and 
 at least one ADC according to  claim 1 ; 
 wherein the plurality of second-side branches consists of two second-side branches that are configured to sample reset voltage signals from pixels in alternating rows of the pixel array. 
 
     
     
       5. An image sensor, comprising:
 an array of pixels; 
 at least one ADC, each comprising (i) a comparator having a first input and a second input; (ii) a first-side branch that comprises a binary-weighted capacitor array and that is configured to sample a voltage signal onto the binary-weighted capacitor array, wherein an output from the binary-weighted capacitor array is coupled to the first input of the comparator; and (iii) a plurality of second-side branches, each second-side branch configured to sample a respective voltage and having a respective output; and wherein the SAR ADC is configured to selectively couple each of the outputs of the second-side branches separately to the second input of the comparator; and 
 control logic that is operable to cause:
 sampling a first signal by a first one of the plurality of second-side branches; 
 sampling a second signal onto the binary-weighted capacitor array; 
 carrying out, based on the first signal and the second signal, a charge redistribution successive approximation A/D conversion using the binary-weighted capacitor array; and 
 while carrying out the charge redistribution successive approximation A/D conversion based on the first and second signals, sampling a third signal onto a second one of the plurality of side branches; 
 wherein the third signal is to be used with a fourth signal sampled onto the binary-weighted capacitor array after carrying out the charge redistribution successive approximation A/D conversion for carrying out a subsequent charge redistribution successive approximation A/D conversion using the binary-weighted capacitor array based on the third and fourth signals. 
 
 
     
     
       6. The image sensor according to  claim 5 , wherein the array of pixels are organized in rows and columns and the image sensor is configured for parallel readout on a plurality of column buses, wherein each column bus is associated with a respective one of said at least one ADCs. 
     
     
       7. The image sensor according to  claim 6 , wherein the number of column buses equals the number of at least one ADCs. 
     
     
       8. The image sensor according to  claim 6 , wherein the number of column buses is greater than the number of at least on ADCs. 
     
     
       9. The image sensor according to  claim 5 , wherein for each of the ADCs the first-side branch that comprises a binary-weighted capacitor array is configured to sample a pixel signal corresponding to photocharge generated by a pixel, and each of the plurality of second-side branches is configured to sample a reset voltage signal corresponding to a pixel of the pixel array.