Array substrate having shift register unit and display device

Abstract

An array substrate and a display device are disclosed. The array substrate (01) comprises a gate electrode driving circuit (10), the gate electrode driving circuit (10) includes at least two stages of shift register units (SR1-SRn), and each stage of the shift register units (SR1-SRn) is connected with a row of gate lines (Gate1-Gaten). The shift register units (SR1-SRn) include driving modules (D1-Dn) and logical modules (L1-Ln); the driving modules (D1-Dn) include a portion located in a display region (100) of the array substrate. The array substrate can solve a problem that a larger size of a driving TFT in a gate driver on array (GOA) circuit is not conducive to a narrow frame design trend of a display panel.

The invention claimed is: 
     
       1. An array substrate, comprising: a gate electrode driving circuit, wherein, the gate electrode driving circuit includes at least two stages of shift register units, each stage of the shift register units is connected with a gate line, and each of the shift register units includes a driving module and a logical module;
 the driving module includes a portion located in a display region of the array substrate; 
 the driving module is connected with the logical module and a first driving signal input terminal, respectively, and the driving module is directly connected with the gate line and under control of a signal output by the logical module, a signal input by the first driving signal input terminal is transmitted to the gate line. 
 
     
     
       2. The array substrate according to  claim 1 , wherein, the logical module is located in a non-display region or the display region of the array substrate. 
     
     
       3. The array substrate according to  claim 2 , wherein the non-display region is a region around the display region on the array substrate. 
     
     
       4. The array substrate according to  claim 2 , further comprising: a plurality of pixel units disposed in the display region, wherein, the driving module includes at least a portion located within the pixel unit. 
     
     
       5. The array substrate according to  claim 2 , wherein, the driving module includes: a first driving transistor and a capacitor,
 the first driving transistor having a gate electrode connected with a first control signal output terminal of the logical module, a first electrode connected with the first driving signal input terminal, and a second electrode connected with the gate line; 
 the capacitor having one end connected with the gate electrode of the first driving transistor, and the other end connected with the second electrode of the first driving transistor. 
 
     
     
       6. The array substrate according to  claim 2 , wherein, the driving module includes at least two driving sub-modules, and the driving sub-module includes a first driving sub-transistor and a sub-capacitor;
 the first driving sub-transistor having a gate electrode connected with a first control signal output terminal of the logical module, a first electrode connected with the first driving signal input terminal, and a second electrode connected with the gate line; 
 the sub-capacitor having one end connected with the gate electrode of the first driving sub-transistor, and the other end connected with the second electrode of the first driving sub-transistor. 
 
     
     
       7. The array substrate according to  claim 1 , further comprising: a plurality of pixel units disposed in the display region, wherein, the driving module includes at least a portion located within the pixel unit. 
     
     
       8. The array substrate according to  claim 7 , wherein, the driving module includes: a first driving transistor and a capacitor,
 the first driving transistor having a gate electrode connected with a first control signal output terminal of the logical module, a first electrode connected with the first driving signal input terminal, and a second electrode connected with the gate line; 
 the capacitor having one end connected with the gate electrode of the first driving transistor, and the other end connected with the second electrode of the first driving transistor. 
 
     
     
       9. The array substrate according to  claim 7 , wherein, the driving module includes at least two driving sub-modules, and the driving sub-module includes a first driving sub-transistor and a sub-capacitor;
 the first driving sub-transistor having a gate electrode connected with a first control signal output terminal of the logical module, a first electrode connected with the first driving signal input terminal, and a second electrode connected with the gate line; 
 the sub-capacitor having one end connected with the gate electrode of the first driving sub-transistor, and the other end connected with the second electrode of the first driving sub-transistor. 
 
     
     
       10. The array substrate according to  claim 1 , wherein, the driving module includes: a first driving transistor and a capacitor,
 the first driving transistor having a gate electrode connected with a first control signal output terminal of the logical module, a first electrode connected with the first driving signal input terminal, and a second electrode connected with the gate line; 
 the capacitor having one end connected with the gate electrode of the first driving transistor, and the other end connected with the second electrode of the first driving transistor. 
 
     
     
       11. The array substrate according to  claim 10 , wherein, the driving module further includes: a second driving transistor,
 the second driving transistor having a gate electrode connected with a second control signal output terminal of the logical module, a first electrode connected with the gate line, and a second electrode connected with a second driving signal input terminal. 
 
     
     
       12. The array substrate according to  claim 1 , wherein, the driving module includes at least two driving sub-modules, and the driving sub-module includes a first driving sub-transistor and a sub-capacitor;
 the first driving sub-transistor having a gate electrode connected with a first control signal output terminal of the logical module, a first electrode connected with the first driving signal input terminal, and a second electrode connected with the gate line; 
 the sub-capacitor having one end connected with the gate electrode of the first driving sub-transistor, and the other end connected with the second electrode of the first driving sub-transistor. 
 
     
     
       13. The array substrate according to  claim 12 , wherein, the driving sub-module further includes: a second driving sub-transistor;
 the second driving sub-transistor having a gate electrode connected with a second control signal output terminal of the logical module, a first electrode connected with the gate line, and a second electrode connected with a second driving signal input terminal. 
 
     
     
       14. The array substrate according to  claim 13 , further comprising: a plurality of pixel units disposed in the display region, wherein, each pixel unit of the display region is provided with one of the driving sub-modules therein. 
     
     
       15. The array substrate according to  claim 14 , wherein, the first driving sub-transistor and the second driving sub-transistor in each stage of the shift register unit are located in two adjacent pixel units of a same row, respectively. 
     
     
       16. The array substrate according to  claim 14 , wherein,
 the logical module includes a first logical sub-module and a second logical sub-module located on both sides of the display region, respectively; 
 wherein, the first logical sub-module of each stage of the shift register unit is connected with the gate electrode of the first driving sub-transistor; 
 the second logical sub-module is connected with the gate electrode of the second driving sub-transistor; 
 the first driving sub-transistor and the second driving sub-transistor are located in an edge region on both sides of a central region of the display region, respectively; 
 wherein, the edge region includes at least one column of pixel units; 
 a number of columns of pixel units in the central region is greater than a number of columns of pixel units in the edge region. 
 
     
     
       17. The array substrate according to  claim 16 , wherein, in two adjacent rows of pixel units located on a same side of the edge region, each of the pixel units in one row corresponds to one of the first driving sub-transistors, and each of the pixel units in the other row corresponds to one of the second driving sub-transistors. 
     
     
       18. The array substrate according to  claim 12 , further comprising: a plurality of pixel units disposed in the display region, wherein, each pixel unit of the display region is provided with one of the driving sub-modules therein. 
     
     
       19. A display device, comprising the array substrate according to  claim 1 .