Physical topology for a power converter

Abstract

A physical topology for receiving top and bottom power electronic switches comprises a top collector trace connected to a positive voltage power supply tab and having a connection area for a collector of a top power electronic switch, a bottom emitter trace connected to a negative voltage power supply tab and having a connection area for an emitter of the bottom power electronic switch, and a middle trace connected to a load tab and having a connection area for an emitter of the top power electronic switch and a connection area for a collector of the bottom power electronic switch. Sampling points are provided on the traces for voltages on the emitters of the top and bottom power electronic switches, on the trace for voltage of the collector of the bottom power electronic switch, and on the negative voltage power supply tab. The topology defines parasitic inductances.

What is claimed is: 
     
       1. A physical topology for receiving top and bottom power electronic switches, each power electronic switch including a collector, a gate and an emitter, the topology comprising:
 a top collector trace connected to a positive voltage power supply tab, the top collector trace having a connection area for the collector of the top power electronic switch; 
 a bottom emitter trace connected to a negative voltage power supply tab, the bottom emitter trace having a connection area for the emitter of the bottom power electronic switch; 
 a unitary and continuous middle trace connected to a load tab, the middle trace having a connection area for the emitter of the top power electronic switch and a connection area for the collector of the bottom power electronic switch, the middle trace forming a top emitter inductance between the connection area for the emitter of the top power electronic switch and the load tab, the middle trace also forming a bottom collector inductance between the load tab and the connection area for the collector of the bottom power electronic switch; 
 a top power electronic switch emitter voltage sampling point located on the middle trace within the connection area for the emitter of the top power electronic switch; 
 a bottom power electronic switch collector voltage sampling point located within a connection area of the middle trace to the load tab; 
 a bottom power electronic switch emitter voltage sampling point located on the bottom emitter trace within the connection area for the emitter of the bottom power electronic switch; and 
 a negative voltage power supply tab sampling point located within a connection area of the bottom emitter trace to the negative voltage power supply tab. 
 
     
     
       2. The topology of  claim 1 , wherein:
 the top collector trace forms a top collector inductance; and 
 the bottom emitter trace forms a bottom emitter inductance. 
 
     
     
       3. The topology of  claim 2 , wherein:
 the top emitter inductance is greater than the top collector inductance and greater than the bottom collector inductance; and 
 the bottom emitter inductance is greater than the top collector inductance and greater than the bottom collector inductance. 
 
     
     
       4. The topology of  claim 1 , wherein:
 the connection area for the collector of the top power electronic switch and the connection area for the collector of the bottom power electronic switch are configured for direct contact with the collectors of the power electronic switches; and 
 the connection area for the emitter of the top power electronic switch and the connection area for the emitter of the bottom power electronic switch are configured for connection to the emitters of the power electronic switches via wires. 
 
     
     
       5. The topology of  claim 1 , wherein:
 the top collector trace is configured for mounting a diode in parallel with the top power electronic switch; and 
 the middle trace is configured for mounting of a diode in parallel with the bottom power electronic switch. 
 
     
     
       6. The topology of  claim 1 , wherein:
 the top collector trace is configured for mounting a plurality of parallelized top power electronic switches; and 
 the middle trace is configured for mounting a plurality of parallelized bottom power electronic switches. 
 
     
     
       7. The topology of  claim 6 , wherein:
 the middle trace includes a groove leading from the top power electronic switch emitter voltage sampling point in a direction toward the load tab to substantially equalize currents in each of the parallelized top power electronic switches; and 
 the bottom emitter trace includes a groove leading from the bottom power electronic switch emitter voltage sampling point in a direction toward the negative voltage power supply tab to substantially equalize currents in each of the parallelized bottom power electronic switches. 
 
     
     
       8. The topology of  claim 1 , wherein the top collector trace, the bottom emitter trace and the middle trace are on a direct bonded copper (DBC) substrate. 
     
     
       9. The topology of  claim 8 , wherein each of the top power electronic switch emitter voltage sampling point, the bottom power electronic switch collector voltage sampling point, the bottom power electronic switch emitter voltage sampling point and the negative voltage power supply tab sampling point is electrically connected to a respective gate driver connection extending from a plane of the DBC substrate and configured for connection to a separate circuit card. 
     
     
       10. The topology of  claim 1 , comprising:
 a top gate trace configured for connection to the gate of the top power electronic switch via one or more wires; and 
 a bottom gate trace configured for connection to the gate of the bottom power electronic switch via one or more wires. 
 
     
     
       11. The topology of  claim 10 , comprising a pair of gate driver connections respectively extending from the top and bottom gate traces and configured for connection to respective top and bottom gate driver outputs. 
     
     
       12. The topology of  claim 1 , wherein the load tab is a phase tab. 
     
     
       13. The topology of  claim 1 , wherein the top and bottom power electronic switches include isolated gate bipolar transistors (IGBT). 
     
     
       14. A power converter, comprising:
 the topology and the top and bottom power electronic switches of  claim 1 ; 
 a top gate driver having a reference electrically connected to the top power electronic switch emitter voltage sampling point and to the bottom power electronic switch collector voltage sampling point; and 
 a bottom gate driver having a reference electrically connected to the bottom power electronic switch emitter voltage sampling point and to the negative voltage power supply tab sampling point. 
 
     
     
       15. The power converter of  claim 14 , wherein:
 the reference of the top gate driver is connected to the top power electronic switch emitter voltage sampling point via a first turn-on diode in parallel with a first resistor, the first turn-on diode being polarized to short the first resistor when a voltage of the top power electronic switch emitter is higher than a voltage of the reference of the top gate driver; 
 the reference of the top gate driver is connected to the bottom power electronic switch collector voltage sampling point via a second resistor; 
 the reference of the bottom gate driver is connected to the bottom power electronic switch emitter voltage sampling point via a second turn-on diode in parallel with a third resistor, the second turn-on diode being polarized to short the third resistor when a voltage of the bottom power electronic switch emitter is higher than a voltage of the reference of the bottom gate driver; 
 the reference of the bottom gate driver is connected to the negative voltage power supply tab sampling point via a fourth resistor. 
 
     
     
       16. A tri-phase power converter comprising three power converters as defined in  claim 14 .