Jitter reduction in clock and data recovery circuits

Abstract

Techniques are disclosed relating to clock and data recovery circuitry. In some embodiments, a slicing circuit may be configured to sample an input signal to generate a first and second sampled data signal. In some embodiments, a phase detector circuit may be configured to compare the phases of the first and second sampled data signals. In some embodiments, a first charge pump may be configured to supply a first current to a circuit node, and a second charge pump may be configured to supply a second current to the circuit node. In some embodiments, a voltage-controlled oscillator may be configured to adjust a frequency of first and second clock signals based on a voltage of the circuit node.

What is claimed is: 
     
       1. An apparatus, comprising:
 a slicing circuit configured to sample an input signal to generate:
 a first sampled data signal based on a first clock signal, and 
 a second sampled data signal based on a second clock signal; 
 
 a phase detector circuit configured to:
 perform a comparison of a phase of the first sampled data signal to a phase of the second sampled data signal; and 
 generate, based on a result of the comparison, a first control signal and a second control signal that are indicative of a difference in phase between the first sampled data signal and the second sampled data signal; 
 
 a control circuit configured to generate a third control signal and a fourth control signal using the first and second control signals; 
 a first charge pump circuit configured to supply a first current to a circuit node using the first and second control signals generated by the phase detector circuit; 
 a second charge pump circuit configured to supply a second current to the circuit node based on the third and fourth control signals, wherein the second current is of opposite polarity to the first current; and 
 a voltage-controlled oscillator circuit configured to adjust a frequency of the first and second clock signals based on a voltage of the circuit node. 
 
     
     
       2. The apparatus of  claim 1 , wherein the first charge pump circuit is configured to supply the first current at a first time, and wherein the control circuit and the second charge pump circuit are configured to supply the second current at a second time later than the first time. 
     
     
       3. The apparatus of  claim 1 , wherein, to generate the third and fourth control signals, the control circuit is further configured to:
 latch a state of the first control signal using the first clock signal to generate the fourth control signal; and 
 latch a state of the second control signal using the first clock signal to generate the third control signal. 
 
     
     
       4. The apparatus of  claim 1 , wherein, to generate the third and fourth control signals, the control circuit is further configured to:
 latch a state of the first control signal using the first clock signal to generate a latched first control signal; 
 latch a state of the second control signal using the first clock signal to generate a latched second control signal; 
 logically combine the second control signal and the latched first control signal to generate the fourth control signal; and 
 logically combine the first control signal and the latched second control signal to generate the third control signal. 
 
     
     
       5. The apparatus of  claim 1 , wherein the second charge pump circuit is further configured to supply a third current to the circuit node using the third control signal, wherein the third current is of a same polarity as the first current; and wherein, to supply the second current to the circuit node, the second charge pump circuit is further configured to supply the second current to the circuit node using the fourth control signal. 
     
     
       6. The apparatus of  claim 1 , wherein a magnitude of the second current is less than a magnitude of the first current, wherein the second current acts to settle the voltage of the circuit node. 
     
     
       7. The apparatus of  claim 1 , further comprising a loop filter circuit configured to attenuate at least one frequency component include in the voltage of the circuit node;
 wherein the input signal includes a plurality of data symbols; and 
 wherein a magnitude of the second current is based on a magnitude of the first current scaled by a factor that is based on a duration of a data symbol of the plurality of data symbols and a time constant of the loop filter circuit. 
 
     
     
       8. The apparatus of  claim 1 , wherein the second charge pump circuit is further configured to adjust a magnitude of the second current. 
     
     
       9. The apparatus of  claim 8 , wherein the second charge pump circuit is configured to adjust the magnitude of the second current based on a settling time of the voltage at the circuit node. 
     
     
       10. A method, comprising:
 generating, by a voltage-controlled oscillator, a first clock signal and a second clock signal based on a voltage of a circuit node; 
 sampling, by a slicing circuit, an input signal using the first clock signal and the second clock signal to generate a first sampled data signal and a second sampled data signal, respectively; 
 comparing, by a phase detector circuit, a phase of the first sampled data signal and a phase of the second sampled data signal; 
 generating, by the phase detector circuit based on a result of the comparing, first and second control signals that are indicative of a difference in phase between the first sampled data signal and the second sampled data signal; 
 generating, by a control circuit, third and fourth control signals using the first and second control signals; 
 modifying, by a first charge pump, a voltage of a circuit node, including by:
 generating a first current using the first and second control signals generated by the phase detector circuit; 
 
 modifying, by a second charge pump, the voltage of the circuit node, including by:
 generating a second current based on the third and fourth control signals, wherein the second current is of opposite polarity to the first current; and 
 
 adjusting, by the voltage-controlled oscillator, a frequency of the first clock signal and the second clock signal based on the voltage of the circuit node. 
 
     
     
       11. The method of  claim 10 , wherein modifying, by the first charge pump, the voltage of the circuit node includes sourcing the first current to the circuit node based on the first control signal; and wherein modifying, by the second charge pump, the voltage of the circuit node includes sinking the second current from the circuit node based on the fourth control signal. 
     
     
       12. The method of  claim 1 , wherein the second current is delayed relative to the first current, wherein the second current acts to settle the voltage of the circuit node. 
     
     
       13. The method of  claim 12 , wherein modifying, by the second charge pump, the voltage of the circuit node further includes:
 sourcing a third current to the circuit node based on the third control signal, wherein the third current is not delayed relative to the first current. 
 
     
     
       14. The method of  claim 13 , wherein a magnitude of the second current is equal to a magnitude of the third current, wherein a polarity of the second current is opposite of a polarity of the third current. 
     
     
       15. The method of  claim 10 , further comprising:
 attenuating, by a loop filter circuit, at least one frequency component include in the voltage of the circuit node; 
 wherein the input signal includes a plurality of data symbols; and 
 wherein a magnitude of the second current is based on a magnitude of the first current scaled by a particular factor, wherein the particular factor is based on a duration of a data symbol of the plurality of data symbols and a time constant of the loop filter circuit. 
 
     
     
       16. A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the hardware integrated circuit according to the design, wherein the design information specifies that the hardware integrated circuit comprises:
 a slicing circuit configured to sample an input signal to generate:
 a first sampled data signal based on a first clock signal, and 
 a second sampled data signal based on a second clock signal; 
 
 a phase detector circuit configured to:
 perform a comparison of a phase of the first sampled data signal and a phase of the second sampled data signal; and 
 generate a first control signal and a second control signal based on a result of the comparison; 
 
 a control circuit configured to generate a third and a fourth control signal using latched versions of the first and second control signals; 
 a first charge pump circuit configured to supply a first current to a circuit node based on the first and second control signals; 
 a second charge pump circuit configured to supply a second current to the circuit node based on the third and fourth control signals, wherein the second current is of opposite polarity to the first current; and 
 a voltage-controlled oscillator circuit configured to adjust a frequency of the first and second clock signals based on a voltage of the circuit node. 
 
     
     
       17. The non-transitory computer readable storage medium of  claim 16 , wherein the first charge pump circuit is configured to supply the first current at a first time, and wherein the second charge pump circuit is configured to supply the second current at a second time later than the first time. 
     
     
       18. The non-transitory computer readable storage medium of  claim 16 , wherein, to generate the third and fourth control signals, the control circuit is further configured to:
 latch a state of the first control signal using the first clock signal to generate the latched version of the first control signal; 
 latch a state of the second control signal using the first clock signal to generate the latched version of the second control signal; 
 logically combine the second control signal and the latched version of the first control signal to generate the fourth control signal; and 
 logically combine the first control signal and the latched version of the second control signal to generate the third control signal. 
 
     
     
       19. The non-transitory computer readable storage medium of  claim 16 , wherein the design information includes mask design data indicative of a circuit design for the control circuit. 
     
     
       20. The non-transitory computer readable storage medium of  claim 16 , wherein the fourth control signal is the latched version of the first control signal, and wherein the third control signal is the latched version of the second control signal.