High performance radio frequency switch

Abstract

A HEMT cell includes two or more gallium nitride (“GaN”) high-electron-mobility transistor (“HEMT”) devices electrically connected in series with each other. The HEMT cell includes a HEMT cell drain, a HEMT cell source and a HEMT cell gate. The HEMT cell drain connects with the drain of a first GaN HEMT device in the series. The HEMT cell source connects with the source of a last GaN HEMT device in the series. The HEMT cell gate connects to a first two-dimensional electron gas (“2DEG”) gate bias resistor that connects with the gate of the first GaN HEMT device. The HEMT cell gate connects to a second 2DEG gate bias resistor that connects with the gate of the second GaN HEMT device. The first and second 2DEG gate bias resistors are located in a 2DEG layer of the HEMT cell. A multi-throw RF switch is also disclosed.

What is claimed is: 
     
       1. A Unit high-electron-mobility transistor (hereinafter “HEMT”) cell, comprising:
 a gallium nitride (hereinafter “GaN”) layer; 
 a two-dimensional electron gas (hereinafter “2DEG”) layer disposed on the GaN layer; 
 a gate dielectric layer disposed on the 2DEG layer; 
 a GaN HEMT having a gate disposed on the gate dielectric layer, a drain adjacent to one side of the gate and a source adjacent to an opposing side of the gate, the GaN HEMT disposed on and including the GaN layer, and the GaN HEMT having its gate coupled to one terminal of a 2DEG gate bias resistor; 
 a HEMT cell gate coupled to another terminal of the 2DEG gate bias resistor; 
 a HEMT cell drain coupled to one terminal of a 2DEG linearity resistor and to the drain of the GaN HEMT; and 
 a HEMT cell source coupled to another terminal of the 2DEG linearity resistor and to the source of the GaN HEMT. 
 
     
     
       2. The Unit HEMT cell of  claim 1 , wherein the GaN layer is disposed on a circuit supporting substrate layer comprising one of a silicon substrate layer and a silicon carbide substrate layer. 
     
     
       3. The Unit HEMT cell of  claim 1 , further comprising an insulative barrier layer interposed between the gate dielectric layer and the 2DEG layer. 
     
     
       4. The Unit HEMT cell of  claim 1 , wherein the 2DEG linearity resistor is disposed in the 2DEG layer. 
     
     
       5. A Unit high-electron-mobility transistor (hereinafter “HEMT”) cell, comprising:
 a gallium nitride (hereinafter “GaN”) layer; 
 a two-dimensional electron gas (hereinafter “2DEG”) layer disposed on the GaN layer; 
 a gate dielectric layer disposed on the 2DEG layer; 
 a plurality of GaN HEMTs disposed on the GaN layer, each GaN HEMT of the plurality of GaN HEMTs being electrically connected in series with each other such that a first GaN HEMT is electrically connected in series with a second GaN HEMT by sharing one of a drain and a source of the first GaN HEMT with one of the other of a drain and a source of the second GaN HEMT; 
 a HEMT cell drain, a HEMT cell source, and a HEMT cell gate; 
 the HEMT cell gate coupled to one terminal of a first 2DEG gate bias resistor and another terminal of the first 2DEG gate bias resistor coupled to a gate of the first GaN HEMT; 
 the HEMT cell gate also coupled to one terminal of a second 2DEG gate bias resistor, wherein another terminal of the second 2DEG gate bias resistor is coupled to a gate of the second GaN HEMT; 
 the drain of the first GaN HEMT coupled to one terminal of a first 2DEG linearity resistor and the source of the first GaN HEMT coupled to another terminal of the first 2DEG linearity resistor; 
 the drain of the second GaN HEMT also coupled to one terminal of a second 2DEG linearity resistor and the source of the second GaN HEMT coupled to another terminal of the second 2DEG linearity resistor; 
 the HEMT cell drain coupled to a remaining unshared drain or source of a very first GaN HEMT in the plurality of GaN HEMTs; and 
 the HEMT cell source coupled to a remaining unshared drain or source of a very last GaN HEMT in the plurality of GaN HEMTs. 
 
     
     
       6. The Unit HEMT cell of  claim 5 , wherein the first 2DEG gate bias resistor, the second 2DEG gate bias resistor, the first 2DEG linearity resistor and the second 2DEG linearity resistor are disposed in the 2DEG layer. 
     
     
       7. The Unit HEMT cell of  claim 5 , wherein each GaN HEMT includes a gate disposed on the gate dielectric layer, and a drain adjacent to one side of the gate and a source adjacent to an opposing side of the gate. 
     
     
       8. The Unit HEMT cell of  claim 5 , wherein the GaN layer is disposed on a circuit supporting substrate layer comprising one of a silicon substrate layer and a silicon carbide substrate layer. 
     
     
       9. The Unit HEMT cell of  claim 5 , further comprising an insulative barrier layer interposed between the gate dielectric layer and the 2DEG layer. 
     
     
       10. The Unit HEMT cell of  claim 6 , wherein the Unit HEMT cell includes at least three GaN HEMTs disposed on the GaN layer and electrically connected in series with each other;
 a third GaN HEMT electrically connected in series with the second GaN HEMT by sharing one of a drain and a source of the third GaN HEMT with one of the other of the drain and the source of the second GaN HEMT that is unshared with the first GaN HEMT; 
 the HEMT cell gate coupled to one terminal of a third 2DEG gate bias resistor, and another terminal of the third 2DEG gate bias resistor coupled to a gate of the third GaN HEMT; and 
 the drain of the third GaN HEMT coupled to one terminal of a third 2DEG linearity resistor, and the source of the third GaN HEMT coupled to another terminal of the third 2DEG linearity resistor, 
 wherein the third 2DEG gate bias resistor and the third 2DEG linearity resistor are disposed in the 2DEG layer. 
 
     
     
       11. A circuit comprising:
 a Unit high-electron-mobility transistor (hereinafter “HEMT”) cell coupled to a controller, the Unit HEMT cell including:
 a gallium nitride (hereinafter “GaN”) layer, 
 a two-dimensional electron gas (hereinafter “2DEG”) layer disposed on the GaN layer, 
 a gate dielectric layer disposed on the 2DEG layer, 
 a plurality of GaN HEMTs including a first GaN HEMT and a second GaN HEMT disposed on the gate dielectric layer, wherein the first GaN HEMT and the second GaN HEMT are configured such that one of a drain and a source of the first GaN HEMT and one of the other of a drain and a source of the second GaN HEMT are connected to a shared node, 
 a HEMT cell drain coupled to a remaining unshared drain or source of the first GaN HEMT, 
 a HEMT cell source coupled to a remaining unshared drain or source of the second GaN HEMT, 
 the drain of the first GaN HEMT coupled to one terminal of a first 2DEG linearity resistor, and the source of the first GaN HEMT coupled to the other terminal of the first 2DEG linearity resistor, 
 the drain of the second GaN HEMT coupled to one terminal of a second 2DEG linearity resistor, and the source of the second GaN HEMT coupled to the other terminal of the second 2DEG linearity resistor, 
 a HEMT cell gate coupled to one terminal of a first 2DEG gate bias resistor, wherein another terminal of the first 2DEG gate bias resistor is coupled to a gate of the first GaN HEMT, 
 the HEMT cell gate also coupled to one terminal of a second 2DEG gate bias resistor, wherein another terminal of the second 2DEG gate bias resistor is coupled to a gate of the second GaN HEMT, and 
 a radio frequency sense circuit having an input terminal coupled to the gate of one GaN HEMT of the plurality of GaN HEMTs and having an output terminal coupled to the controller, wherein the radio frequency sense circuit outputs a feedback signal in response to detecting a high power radio frequency signal present in at least one of the drain and the source of the one GaN HEMT; and 
 
 the controller including:
 a charge pump having an input terminal coupled to the output terminal of the radio frequency sense circuit and having an output terminal, and 
 a negative voltage level shifter having a first input terminal coupled to the output terminal of the charge pump, a second input terminal coupled to the output terminal of the radio frequency sense circuit and having an output terminal coupled to the HEMT cell gate, 
 
 wherein, in response to the feedback signal, the controller outputs one of a high-level negative bias voltage signal and a low-level negative bias voltage signal to the HEMT cell gate. 
 
     
     
       12. The circuit of  claim 11 , wherein, in response to the radio frequency sense circuit detecting the high power radio frequency signal present in at least one of the drain and the source of the one GaN HEMT, the controller outputs the high-level negative bias voltage signal thereby increasing isolation between the drain and source of each GaN HEMT of the plurality of GaN HEMTs of the Unit HEMT cell. 
     
     
       13. The circuit of  claim 11 , wherein the GaN layer is disposed on a substrate, and the controller is disposed on the substrate. 
     
     
       14. The circuit of  claim 11 , wherein the controller includes a logic gate having one input terminal receiving the feedback signal and having another input terminal receiving a mode signal from a radio, and having an output terminal coupled to the input terminal of the charge pump and to the second input terminal of the negative voltage level shifter, wherein the controller outputs the one of a high-level negative bias voltage signal and a low-level negative bias voltage signal to the HEMT cell gate based on a combination of the feedback signal and the mode signal.