Land grid array package extension

Abstract

BGA packages with a LGA package extension. First lands on a substrate are populated with solder balls, while only solder paste is dispensed on second lands that are surrounded by the first lands. Differences in solder stand-off may accommodate non-planarity in a package or the insertion of an LGA extension component, such as an IC or one or more discrete devices. Where an LGA extension component is attached to the second lands, solder paste may be further dispensed on third lands located on a package-side of the extension component. A BGA package is then attached to the first lands and third lands. The larger volume BGA solder connections maintaining mechanical reliability, particularly where the solder ball interconnects form a perimeter surrounding the low-volume solder interconnects.

What is claimed is: 
     
       1. A microelectronic device package assembly, comprising:
 a substrate including first lands and second lands; 
 a first component having a first side attached to the first lands by first solder features; and 
 a second component stacked over the first component, the second component having a first side attached to the second lands by second solder features, wherein:
 the first solder features have a smaller stand-off height than the second solder features, and wherein the first solder features have a voiding area of at least 5%, and wherein voiding is substantially absent within the second solder features; and 
 a difference in stand-off height between the first and second solder features accommodates a thickness of the first component between the substrate and the second component. 
 
 
     
     
       2. The package assembly of  claim 1 , wherein the second lands form a perimeter surrounding the first lands, and wherein the perimeter comprises a 2D array of the second lands adjacent to each side of the first component. 
     
     
       3. The package assembly of  claim 1 , wherein a thickness of the first component summed with a stand-off height of the first solder features is less than a stand-off height of the second solder features. 
     
     
       4. The package assembly of  claim 3 , wherein:
 the second component is electrically coupled to the first component by third solder features, wherein the third solder features have a smaller stand-off height than the second solder features; and 
 the thickness of the first of the components summed with the stand-off height of the first solder features and a stand-off height of the third solder features is equal to the stand-off height of the second solder features. 
 
     
     
       5. The package assembly of  claim 4 , wherein:
 the stand-off height of the second solder features is at least 200 μm; and 
 the stand-off height of the first and third solder features is no more than 100 μm. 
 
     
     
       6. The package assembly of  claim 4 , wherein the first component comprises one or more capacitors having a first electrode electrically coupled to the substrate through one or more of the first solder features and a second electrode electrically coupled to the second component through one or more of the third solder features. 
     
     
       7. The package assembly of  claim 1 , wherein a first component comprises an IC chip or a discrete device. 
     
     
       8. The package assembly of  claim 7 , wherein:
 the substrate comprises a printed circuit board (PCB); and 
 the second component comprises one or more packaged IC chips. 
 
     
     
       9. The package assembly of  claim 8 , further comprising a die-attach film (DAF) or die-attach paste (DAP) between the first and second components. 
     
     
       10. The package assembly of  claim 1 , wherein:
 the substrate comprises a printed circuit board (PCB); 
 the first component comprises a package substrate having a chip side to which one or more IC chips are attached, and a land side, opposite the chip side, that is electrically coupled to the first component, and to the PCB; 
 the land side of the package substrate has a first area that is recessed from a second area; 
 the first area is electrically coupled to the first component and the first component is coupled to the PCB by the first solder features; and 
 the second area is electrically coupled to the PCB by the second solder features. 
 
     
     
       11. The package assembly of  claim 1 , wherein:
 the substrate comprises a printed circuit board (PCB) or a package substrate; 
 the second component comprises a memory chip attached to the first lands by first solder features having a first stand-off height; 
 the second component comprises a microprocessor attached to the second lands by the second solder features, the second features having a second stand-off height that is at least equal to the first stand-off height summed with a thickness of the memory chip; and 
 the memory chip is between the microprocessor and the PCB or the package substrate. 
 
     
     
       12. The package assembly of  claim 11 , wherein the memory chip comprises an eDRAM chip. 
     
     
       13. The package assembly of  claim 11 , wherein:
 the memory chip has a first side attached to the first lands, and a second side, opposite the first side, attached to the microprocessor with a die-attach film (DAF), or third solder features; 
 the DAF or third solder features have a third stand-off height; and 
 the second stand-off height is equal to the first stand-off height summed with the third stand-off height and the thickness of the memory chip. 
 
     
     
       14. The package assembly of  claim 13 , wherein the memory chip is attached to the microprocessor with the third solder features. 
     
     
       15. The package assembly of  claim 14 , wherein:
 the third solder features have voids of at least 5% of a solder area of the first solder features; and 
 the second solder features have a voiding area that is less than that of the first and third solder features.