Semiconductor memory device

Abstract

A semiconductor memory device includes a first semiconductor well of a first conductivity type in a memory cell region and a contact region of a substrate, a second semiconductor well of a second conductivity type in the first semiconductor well in the contact region, a plurality of electrode films stacked on the first semiconductor well and spaced from one another in a first direction, the plurality of electrode films extending in a second direction within the memory cell region into the contact region, a first semiconductor pillar extending in the second direction through the plurality of electrode films in the memory cell region, a second semiconductor pillar extending in the second direction through at least one electrode film in the contact region, a charge storage film between the first semiconductor pillar and each electrode film, an insulating film between the second semiconductor pillar and the at least one electrode film.

What is claimed is: 
     
       1. A semiconductor memory device, comprising:
 a first semiconductor well of a first conductivity type in a memory cell region and a contact region of a substrate; 
 a second semiconductor well of a second conductivity type in the first semiconductor well in the contact region; 
 a plurality of electrode films stacked on the first semiconductor well and spaced from one another in a first direction, the plurality of electrode films extending in a second direction within the memory cell region into the contact region; 
 a first semiconductor pillar extending in the second direction through the plurality of electrode films in the memory cell region; 
 a second semiconductor pillar extending in the second direction through at least one electrode film of the plurality in the contact region; 
 a charge storage film between the first semiconductor pillar and each electrode film of the plurality; 
 an insulating film between the second semiconductor pillar and the at least one electrode film of the plurality; and 
 a third semiconductor well of the first conductivity type in the second semiconductor well, the second semiconductor well being between the first and third semiconductor wells, wherein 
 a lower end portion of the second semiconductor pillar along the first direction directly contacts the third semiconductor well. 
 
     
     
       2. The semiconductor memory device according to  claim 1 , further comprising:
 a conductive plate on the first semiconductor well and adjacent to the plurality of electrode films in a third direction within both the memory cell region and the contact region, wherein 
 the conductive plate is electrically connected to the first semiconductor well. 
 
     
     
       3. The semiconductor memory device according to  claim 1 , wherein the first conductivity type is a p type, and the second conductivity type is an n type. 
     
     
       4. The semiconductor memory device according to  claim 1 , wherein the second semiconductor pillar has a lower portion and an upper portion on the lower portion, the lower portion extends through a lowermost electrode film of the plurality of electrode film and is coated with an insulating film, and the upper portion comprises a semiconductor core coated with a charge trap film. 
     
     
       5. A semiconductor memory device, comprising:
 a first semiconductor well of a first conductivity type in a memory cell region and a contact region of a substrate; 
 a second semiconductor well of a second conductivity type in the first semiconductor well in the contact region; 
 a plurality of electrode layers stacked on a substrate in a first direction, spaced from each in the first direction, and extending in a second direction from the memory cell region into the contact region; 
 a first semiconductor pillar in the memory cell region and extending through the plurality of electrode layers in a third direction to the first semiconductor well, a charge trap film coating an outer surface of the first semiconductor pillar between the first semiconductor pillar and each electrode layer of the plurality; 
 a second semiconductor pillar in the contact region extending in the third direction through at least one electrode layer in the plurality to the substrate, an insulating film coating an outer surface of the second semiconductor pillar between the second semiconductor pillar and the at least one electrode layer; and 
 a third semiconductor well of the first conductivity type in the second semiconductor well, the second semiconductor well being between the first and third semiconductor wells, wherein 
 a lower end portion of the second semiconductor pillar along the first direction directly contacts the third semiconductor well. 
 
     
     
       6. The semiconductor memory device according to  claim 5 , further comprising:
 a conductive plate electrically connected to the first semiconductor well and adjacent to the plurality of electrode films within both the memory cell region and the contact region. 
 
     
     
       7. The semiconductor memory device according to  claim 5 , wherein the first conductivity type is a p type, and the second conductivity type is an n type. 
     
     
       8. A semiconductor memory device, comprising:
 a first semiconductor well of a first conductivity type in a memory cell region and a contact region of a substrate; 
 a second semiconductor well of a second conductivity type in the first semiconductor well in the contact region; 
 a plurality of electrode films stacked on the first semiconductor well and spaced from one another in a first direction, the plurality of electrode films extending in a second direction within the memory cell region into the contact region; 
 a first semiconductor pillar extending in the second direction through the plurality of electrode films in the memory cell region; 
 a second semiconductor pillar extending in the second direction through at least one electrode film of the plurality in the contact region; 
 a charge storage film between the first semiconductor pillar and each electrode film of the plurality; 
 an insulating film between the second semiconductor pillar and the at least one electrode film of the plurality; 
 an interlayer insulating film between the substrate and the first semiconductor well in the first direction, wherein 
 the first conductivity type is an n type, and the second conductivity type is a p type, 
 the first semiconductor pillar contacts the first semiconductor well, and 
 the second semiconductor pillar contacts the second semiconductor well. 
 
     
     
       9. The semiconductor memory device according to  claim 8 , wherein the second semiconductor pillar has a lower portion and an upper portion on the lower portion, the lower portion extends through a lowermost electrode film of the plurality of electrode film and is coated with an insulating film, and the upper portion comprises a semiconductor core coated with a charge trap film.