Flexible architecture and instruction for advanced encryption standard (AES)

Abstract

A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

The invention claimed is: 
     
       1. A system comprising:
 a processor comprising:
 a plurality of cores; 
 a level 1 (L1) instruction cache to store a plurality of instructions, the plurality of instructions to include a plurality of Advanced Encryption Standard (AES) instructions of an instruction set of the processor, the instruction set of the processor including a Single Instruction Multiple Data (SIMD) instruction set, wherein the plurality of AES instructions include a first AES instruction for a round of an AES decryption operation, a second AES instruction for a final round of the AES decryption operation, a third AES instruction for a round of an AES encryption operation, and a fourth AES instruction for a final round of the AES encryption operation, and wherein the plurality of AES instructions each comprise a different opcode; 
 an L1data cache; 
 instruction fetch logic to fetch instructions from the L1 instruction cache; 
 decode logic to decode instructions including the first AES instruction; 
 a first 128-bit source register to store a round key to be used for the round of the AES decryption operation; 
 a second 128-bit source register to store input data to be decrypted by the round of the AES decryption operation; 
 a plurality of ports, each associated with one or more corresponding execution resources, to support parallel execution of integer and floating point operations; 
 an execution unit including AES execution logic to execute the first AES instruction of the instruction set of the processor to perform the round of the AES decryption operation, 
 wherein the execution unit is to execute microcode, determined from the decode of the first AES instruction, to execute the first AES instruction, the AES decryption operation to use the round key from the first 128-bit source register to decrypt the input data from the second 128-bit source register and to store a result of the round of the AES decryption operation in a 128-bit destination register, 
 wherein the round of the AES decryption operation is to include:
 a substitution operation to be performed on the input data, the substitution operation to use an inverse substitution box (S-box) lookup; 
 an inverse Shift Rows operation; 
 an inverse Mix Columns operation; and 
 an Add Round Key operation in which an exclusive OR function is to use data from the round key; and 
 
 a retirement unit; 
 
 a system memory comprising a multiple data rate dynamic random access memory coupled to the processor over one or more interconnects; 
 one or more storage devices coupled to the processor; and 
 an input/output (I/O) controller to couple the processor to one or more devices, the one or more devices to include the one or more storage devices, wherein at least one of the one or more storage devices is to be coupled to the processor over at least one Serial Attached Small Computer System Interface (SAS). 
 
     
     
       2. The system of  claim 1 , wherein the one or more storage devices are to be arranged as a Redundant Array of Independent Disks (RAID). 
     
     
       3. The system of  claim 1 , further comprising at least one network interface coupled to the processor to process data packets. 
     
     
       4. The system of  claim 1 , further comprising at least one network interface coupled to the processor to process data packets, and wherein the one or more storage devices are to be arranged as a Redundant Array of Independent Disks (RAID). 
     
     
       5. The system of  claim 1 , wherein the processor is a general-purpose processor, and wherein the plurality of AES instructions include more than four AES instructions that each comprise a different opcode. 
     
     
       6. A system comprising:
 a processor comprising:
 a level 1 (L1) instruction cache to store a plurality of instructions, the plurality of instructions to include a plurality of Advanced Encryption Standard (AES) instructions of an instruction set of the processor, the instruction set of the processor including a Single Instruction Multiple Data (SIMD) instruction set, wherein the plurality of AES instructions include a first AES instruction for a round of an AES decryption operation, a second AES instruction for a final round of the AES decryption operation, a third AES instruction for a round of an AES encryption operation, and a fourth AES instruction for a final round of the AES encryption operation, and wherein the plurality of AES instructions each comprise a different opcode; 
 an L1data cache; 
 a decode unit to decode instructions including the first AES instruction; 
 a first 128-bit source register to store a round key to be used for the round of the AES decryption operation; 
 a second 128-bit source register to store input data to be decrypted by the round of the AES decryption operation; 
 a plurality of ports, each associated with one or more corresponding execution resources, to support parallel execution of integer and floating point operations; 
 an execution unit to perform the first AES instruction of the instruction set of the processor to perform the round of the AES decryption operation, wherein the execution unit is to execute microcode, determined from the decode of the first AES instruction, to execute the first AES instruction, the AES decryption operation to use the round key from the first 128-bit source register to decrypt the input data from the second 128-bit source register and to store a result of the round of the AES decryption operation in a 128-bit destination register, 
 wherein the round of the AES decryption operation is to include:
 a substitution operation to be performed on the input data, the substitution operation to use an inverse substitution box (S-box) lookup; 
 an inverse Shift Rows operation; 
 an inverse Mix Columns operation; and 
 an Add Round Key operation in which an exclusive OR function is to use data from the round key; and 
 
 a retirement unit; 
 
 a system memory comprising a multiple data rate dynamic random access memory coupled to the processor over one or more interconnects; 
 one or more storage devices coupled to the processor; and 
 an input/output (I/O) controller to couple the processor to one or more devices, the one or more devices to include the one or more storage devices, wherein at least one of the one or more storage devices is to be coupled to the processor over at least one Serial Attached Small Computer System Interface (SAS). 
 
     
     
       7. The system of  claim 6 , wherein the one or more storage devices are to be arranged as a Redundant Array of Independent Disks (RAID). 
     
     
       8. The system of  claim 6 , further comprising at least one network interface coupled to the processor to process data packets. 
     
     
       9. The system of  claim 6 , further comprising at least one network interface coupled to the processor to process data packets, and wherein the one or more storage devices are to be arranged as a Redundant Array of Independent Disks (RAID). 
     
     
       10. The system of  claim 6 , wherein the processor is a general-purpose processor, and wherein the plurality of AES instructions include more than four AES instructions that each comprise a different opcode. 
     
     
       11. The processor of  claim 6 , wherein the execution unit is to have a different execution port to perform the first AES instruction than one or more other execution ports that are to be used for AES key scheduling operations. 
     
     
       12. A system comprising:
 a processor comprising:
 a plurality of cores; 
 a level 1 (L1) instruction cache to store a plurality of instructions of an instruction set of the processor, the instruction set of the processor including a Single Instruction Multiple Data (SIMD) instruction set, the plurality of instructions to include a first Advanced Encryption Standard (AES) instruction, wherein the first AES instruction has a bit with a value of one to indicate that encryption is to be performed instead of a value of zero which would indicate that decryption is to be performed; 
 an L1data cache; 
 instruction fetch logic to fetch instructions from the L1 instruction cache; 
 decode logic to decode instructions including the first AES instruction; 
 a first 128-bit source register to store a round key to be used for a round of an AES decryption operation; 
 a second 128-bit source register to store input data to be decrypted by the round of the AES decryption operation; 
 a plurality of ports, each associated with one or more corresponding execution resources, to support parallel execution of integer and floating point operations; 
 an execution unit including AES execution logic to execute the first AES instruction of the instruction set of the processor to perform the round of the AES decryption operation, 
 wherein the execution unit is to execute microcode, determined from the decode of the first AES instruction, to execute the first AES instruction, the AES decryption operation to use the round key from the first 128-bit source register to decrypt the input data from the second 128-bit source register and to store a result of the round of the AES decryption operation in a 128-bit destination register, 
 wherein the round of the AES decryption operation is to include:
 a substitution operation to be performed on the input data, the substitution operation to use an inverse substitution box (S-box) lookup; 
 an inverse Shift Rows operation; 
 an inverse Mix Columns operation; and 
 an Add Round Key operation in which an exclusive OR function is to use data from the round key; and 
 
 a retirement unit; 
 
 a system memory comprising a multiple data rate dynamic random access memory coupled to the processor over one or more interconnects; 
 one or more storage devices coupled to the processor; and 
 an input/output (I/O) controller to couple the processor to one or more devices, the one or more devices to include the one or more storage devices, wherein at least one of the one or more storage devices is to be coupled to the processor over at least one Serial Attached Small Computer System Interface (SAS).