Display substrate, its manufacturing method and display device

Abstract

The present disclosure provides a display substrate, its manufacturing method, and a display device. The method includes a step of forming a plurality of TFTs. The method further includes steps of: forming a lattice matching layer on a substrate so as to deposit AlN thereon; depositing an AlN layer on the lattice matching layer by low-temperature pulse magnetron sputtering; and forming on the AlN layer GaN LEDs each including an n-type GaN layer, a multilayered quantum well structure and a p-type GaN layer and corresponding to one of the TFTs.

What is claimed is: 
     
       1. A method for manufacturing a display substrate, comprising a step of forming a plurality of thin film transistors (TFTs), wherein the method further comprises steps of:
 forming a lattice matching layer on a substrate so as to deposit aluminum nitride (AlN) on the lattice matching layer; 
 depositing an AlN layer on the lattice matching layer by low-temperature pulse magnetron sputtering; and 
 forming on the AlN layer gallium nitride (GaN) light-emitting diodes (LEDs) each including an n-type GaN layer, a multilayered quantum well structure and a p-type GaN layer and corresponding to one of the TFTs, 
 wherein the lattice matching layer is a graphene layer; 
 wherein the step of forming the plurality of TFTs comprises:
 providing a base substrate; 
 forming a TFT including a gate electrode, a source electrode and a drain electrode on the base substrate; and 
 forming a passivation layer having a surface roughness not greater than a predetermined value on the base substrate with the TFT, 
 
 the step of forming the lattice matching layer on the substrate comprises:
 forming the graphene layer including a first via-hole on the passivation layer, 
 the step of depositing the AlN layer on the lattice matching layer by low-temperature pulse magnetron sputtering comprises: 
 depositing the AlN layer on the graphene layer by low-temperature pulse magnetron sputtering, and 
 the step of forming on the AlN layer the GaN LEDs each including the n-type GaN layer, the multilayered quantum well structure and the p-type GaN layer comprises: 
 forming the n-type GaN layer on the AlN layer, and forming a second via-hole penetrating through the passivation layer, the AlN layer and the n-type GaN layer and located in the first via-hole; 
 forming a via-hole electrode configured to connect the n-type GaN layer to the drain electrode through the second via-hole; and 
 forming a pixel definition layer, the multilayered quantum well structure, the p-type GaN layer and a transparent electrode layer. 
 
 
     
     
       2. The method according to  claim 1 , wherein prior to the step of depositing the AlN layer on the lattice matching layer by low-temperature pulse magnetron sputtering, the method further comprises:
 subjecting the graphene layer to heat treatment in vacuum or nitrogen at a temperature of 500 to 600° C. 
 
     
     
       3. The method according to  claim 1 , wherein the step of forming the graphene layer including the first via-hole on the passivation layer comprises:
 depositing single-layered or multilayered graphene on a copper foil, laminating the graphene layer on the copper foil onto the base substrate with the passivation layer so as to attach the graphene layer onto the passivation layer, and etching off the copper foil by an etchant, so as to form the graphene layer including the first via-hole by plasma etching; or 
 depositing single-layered or multilayered graphene onto the copper foil, patterning the graphene layer by plasma etching, and transferring the patterned graphene layer onto the base substrate with the passivation layer, so as to form the graphene layer including the first via-hole on the passivation layer; or 
 etching the copper foil with the etchant to pattern the copper foil, depositing single-layered or multilayered graphene onto the patterned copper foil, and transferring the graphene layer on the patterned copper foil onto the base substrate with the passivation layer, so as to form the graphene layer including the first via-hole on the passivation layer. 
 
     
     
       4. The method according to  claim 1 , wherein the step of depositing the AlN layer on the lattice matching layer by low-temperature pulse magnetron sputtering comprises:
 sputtering an Al target with a bipolar pulse in a working gas at a temperature of 500 to 600° C. and at a pressure of 0.3 to 0.6 Pa, so as to form the AlN layer having a thickness of 30 to 100 nm, wherein the pulse has a frequency of 10 to 100 kHz, a duration of an on-state signal is 1/10 to ½ of a duration of an off-state signal, the working gas is a mixture of N 2  and Ar, or NH 3  and Ar, and a deposition rate is 500 to 3000 nm/h. 
 
     
     
       5. The method according to  claim 1 , wherein the step of forming the n-type GaN layer comprises:
 forming the n-type GaN having a thickness of 1000 to 1500 nm on the AlN layer through a first mask plate by low-temperature pulse magnetron sputtering, 
 wherein the first mask plate comprises an aperture corresponding to a region where the n-type GaN layer is deposited, and a target is Ga doped with Si or O. 
 
     
     
       6. The method according to  claim 1 , wherein the step of forming the multilayered quantum well structure comprises:
 depositing sequentially a GaN layer having a thickness of 8 to 10 nm and an indium gallium nitride (InGaN) layer having a thickness of 3 to 5 nm on the n-type GaN layer using undoped Ga and In-doped Ga as targets through a second mask plate by low-temperature pulse magnetron sputtering, and repeating the deposition procedure five times, so as to form the multilayered quantum well structure, 
 wherein the second mask plate comprises an aperture corresponding to a region where the multilayered quantum well structure is deposited. 
 
     
     
       7. The method according to  claim 1 , wherein the step of forming the p-type GaN layer comprises:
 forming the p-type GaN layer having a thickness of 500 to 800 nm on the multilayered quantum well structure through a third mask plate by low-temperature pulse magnetron sputtering, 
 wherein the third mask plate comprises an aperture corresponding to a region where the p-type GaN layer is deposited, and a target is Mg-doped Ga. 
 
     
     
       8. The method according to  claim 1 , wherein the substrate is a glass substrate. 
     
     
       9. A method for manufacturing a display substrate, comprising a step of forming a plurality of thin film transistors (TFTs), wherein the method further comprises steps of:
 forming a lattice matching layer on a substrate so as to deposit aluminum nitride (AlN) on the lattice matching layer; 
 depositing an AlN layer on the lattice matching layer by low-temperature pulse magnetron sputtering; and 
 forming on the AlN layer gallium nitride (GaN) light-emitting diodes (LEDs) each including an n-type GaN layer, a multilayered quantum well structure and a p-type GaN layer and corresponding to one of the TFTs, 
 wherein the lattice matching layer is a graphene layer; 
 wherein the step of forming the lattice matching layer on the substrate comprising:
 providing a base substrate; 
 depositing a first transparent conductive layer on the base substrate; and 
 forming the graphene layer on the first transparent conductive layer, 
 
 the step of depositing the AlN layer on the lattice matching layer by low-temperature pulse magnetron sputtering comprises:
 depositing the AlN layer onto the graphene layer by low-temperature pulse magnetron sputtering, 
 
 the step of forming on the AlN layer the GaN LEDs each including the n-type GaN layer, the multilayered quantum well structure and the p-type GaN layer comprises:
 forming the n-type GaN layer, a pixel definition layer, the multilayered quantum well structure, the p-type GaN layer and a second transparent conductive layer sequentially on the AlN layer; 
 etching the pixel definition layer, the multilayered quantum well structure, the p-type GaN layer and the second transparent conductive layer at a channel region, so as to expose the n-type GaN layer at the channel region; 
 etching the n-type GaN layer, the AlN layer and the graphene layer at the channel region, so as to form a first electrode hole penetrating through the n-type GaN layer, the AlN layer and the graphene layer; and 
 forming a first electrode configured to connect the n-type GaN layer to the first transparent conductive layer through the first electrode hole, and 
 the step of forming the plurality of TFTs comprises: 
 forming a planarization layer, and forming the TFT including a gate electrode, a gate insulation layer, a source electrode and a drain electrode on the planarization layer; 
 forming a second electrode hole penetrating through the gate insulation layer and the planarization layer; 
 forming a second electrode configured to connect the p-type GaN layer to the drain electrode through the second electrode hole; and 
 forming a passivation layer. 
 
 
     
     
       10. The method according to  claim 9 , wherein the step of forming the graphene layer on the first transparent conductive layer comprises:
 depositing single-layered or multilayered graphene onto a copper foil, laminating the graphene layer on the copper foil onto the base substrate with the first transparent conductive layer so as to attach the graphene layer onto the first transparent conductive layer, and etching off the copper foil by an etchant; or 
 depositing single-layered or multilayered graphene onto the copper foil, and transferring the graphene layer onto the base substrate with the first transparent conductive layer, so as to form the graphene layer on the first transparent conductive layer. 
 
     
     
       11. The method according to  claim 9 , wherein the step of forming the n-type GaN layer comprises:
 forming the n-type GaN having a thickness of 1000 to 1500 nm on the AlN layer through a first mask plate by low-temperature pulse magnetron sputtering, 
 wherein the first mask plate comprises an aperture corresponding to a region where the n-type GaN layer is deposited, and a target is Ga doped with Si or O. 
 
     
     
       12. The method according to  claim 9 , wherein the step of forming the multilayered quantum well structure comprises:
 depositing sequentially a GaN layer having a thickness of 8 to 10 nm and an InGaN layer having a thickness of 3 to 5 nm on the n-type GaN layer using undoped Ga and In-doped Ga as targets through a second mask plate by low-temperature pulse magnetron sputtering, and repeating the deposition procedure five times, so as to form the multilayered quantum well structure, 
 wherein the second mask plate comprises an aperture corresponding to a region where the multilayered quantum well structure is deposited. 
 
     
     
       13. The method according to  claim 10 , wherein the step of forming the p-type GaN layer comprises:
 forming the p-type GaN layer having a thickness of 500 to 800 nm on the multilayered quantum well structure through a third mask plate by low-temperature pulse magnetron sputtering, 
 wherein the third mask plate comprises an aperture corresponding to a region where the p-type GaN layer is deposited, and a target is Mg-doped Ga. 
 
     
     
       14. The method according to  claim 9 , wherein prior to the step of depositing the AlN layer on the lattice matching layer by low-temperature pulse magnetron sputtering, the method further comprises:
 subjecting the graphene layer to heat treatment in vacuum or nitrogen at a temperature of 500 to 600° C. 
 
     
     
       15. The method according to  claim 9 , wherein the substrate is a glass substrate.