Vertical DMOS transistor

Abstract

A transistor includes a semiconductor body; a first gate electrode formed on a first portion of the semiconductor body and a second gate electrode formed on a second portion of the semiconductor body. A drain region is formed on a first side of the first gate electrode and a first source region is formed on a second side of the first gate electrode. The drain region is formed on a first side of the second gate electrode and a second source region is formed on a second side of the second gate electrode. A trench is formed in the semiconductor body and positioned in the drain region. A doped sidewall region is formed in the semiconductor body along the sidewall of the trench outside of the trench. The doped sidewall region is in electrical contact with the drain region and forms a vertical drain current path for the transistor.

What is claimed is: 
     
       1. A transistor, comprising:
 a semiconductor body of a first conductivity type; 
 a first gate electrode formed on a first portion of the semiconductor body and insulated from the semiconductor body by a gate dielectric layer, a drain region of a second conductivity type formed on a first side of the first gate electrode and a first source region of the second conductivity type formed on a second side of the first gate electrode, the second side opposite the first side; 
 a second gate electrode formed on a second portion of the semiconductor body and insulated from the semiconductor body by the gate dielectric layer, the drain region being formed on a first side of the second gate electrode and a second source region of the second conductivity type formed on a second side of the second gate electrode; 
 a trench formed in the semiconductor body and positioned in the drain region, the trench being lined with a thin dielectric layer as a sidewall dielectric layer, the trench being filled with a bottom dielectric layer at a lower portion of the trench and a conductive layer above the bottom dielectric layer, the conductive layer being electrically connected to the gate electrode, wherein the first and second portions of the semiconductor body are on opposite sides of the trench; and 
 a doped sidewall region of the second conductivity type formed in the semiconductor body along the sidewall of the trench outside of the trench, the doped sidewall region being in electrical contact with the drain region and forming a vertical drain current path for the transistor, the drain current of the transistor flowing in the doped sidewall region in the semiconductor body outside of the trench. 
 
     
     
       2. The transistor of  claim 1 , wherein the conductive layer formed in the trench is electrically connected to the first and second gate electrodes to form a trench conductive field plate for the vertical drain current path, the field plate being biased to an accumulation mode when the transistor is turned on to reduce the resistivity of the vertical drain current path. 
     
     
       3. The transistor of  claim 1 , wherein the thin dielectric layer comprises a thin oxide layer and the conductive layer in the trench comprises a polysilicon layer. 
     
     
       4. The transistor of  claim 1 , wherein the trench is positioned in the drain region and the drain region has a first length between the trench and first gate electrode and a second length between the trench and the second gate electrode, the first length does not equal the second length. 
     
     
       5. The transistor of  claim 1 , wherein the trench is positioned in the drain region and the drain region has a first length between the trench and first gate electrode and a second length between the trench and the second gate electrode, the first length being the same as the second length. 
     
     
       6. The transistor of  claim 1 , wherein the semiconductor body comprises:
 a substrate of the first conductivity type; 
 a buried layer of the second conductivity type formed on the substrate; and 
 an epitaxial layer formed on the substrate and a well region of the first conductivity type formed in the epitaxial layer, 
 wherein the first and second portions of the semiconductor body and the trench are formed in the well region and the trench reaches at least the buried layer and the drain current of the transistor flows through the doped sidewall region to the buried layer. 
 
     
     
       7. The transistor of  claim 6 , further comprising:
 a second trench formed in the semiconductor body remote from the trench and reaching at least the buried layer, the second trench being lined with a second sidewall dielectric layer and filled with a second conductive layer; and 
 a trench bottom doped region of the second conductivity type being formed in the semiconductor body beneath the second trench, 
 wherein the second conductive layer of the second trench is in electrical contact with the trench bottom doped region and the buried layer, the second conductive layer forming a trench drain electrode conducting the drain current of the transistor. 
 
     
     
       8. The transistor of  claim 7 , wherein the second conductive layer comprises one of aluminum or tungsten. 
     
     
       9. The transistor of  claim 1 , wherein the transistor comprises a double-diffused MOS transistor with a lateral channel under the first and second gate electrodes and the drain current flows from the drain region to the vertical drain current path in the doped sidewall region along the sidewall of the trench. 
     
     
       10. The transistor of  claim 1 , wherein the drain region is more heavily doped than the doped sidewall region. 
     
     
       11. The transistor of  claim 1 , wherein the first conductivity type comprises P-type conductivity and the second conductivity type comprises N-type conductivity. 
     
     
       12. A transistor, comprising:
 a semiconductor body of a first conductivity type; 
 a first gate electrode formed on a first portion of the semiconductor body and insulated from the semiconductor body by a gate dielectric layer, a drain region of a second conductivity type formed on a first side of the first gate electrode and a first source region of the second conductivity type formed on a second side of the first gate electrode, the second side opposite the first side; 
 a second gate electrode formed on a second portion of the semiconductor body and insulated from the semiconductor body by the gate dielectric layer, the drain region being formed on a first side of the second gate electrode and a second source region of the second conductivity type formed on a second side of the second gate electrode; 
 a trench formed in the semiconductor body and positioned in the drain region, the trench being lined with a thin dielectric layer as a sidewall dielectric layer; 
 a doped sidewall region of the second conductivity type formed in the semiconductor body along the sidewall of the trench outside of the trench, the doped sidewall region being in electrical contact with the drain region and forming a vertical drain current path for the transistor, the drain current of the transistor flowing in the doped sidewall region in the semiconductor body outside of the trench; 
 a trench bottom doped region of the second conductivity type formed in the semiconductor body beneath the trench and in electrical contact with the doped sidewall region formed in the semiconductor body along the sidewall of the trench, 
 wherein the trench is filled at an outer perimeter with a bottom dielectric layer at a lower portion of the trench and a first conductive layer above the bottom dielectric layer, and the remaining portion of the trench is filled with a second conductive layer in electrical contact with the trench bottom doped region, the second conductive layer being electrically insulated from the first conductive layer by a dielectric layer, the second conductive layer forming a trench drain electrode, the drain current of the transistor flowing in the vertical drain current path is directed to the trench bottom doped region and to the trench drain electrode. 
 
     
     
       13. The transistor of  claim 12 , wherein the first conductive layer formed in the trench is electrically connected to the first and second gate electrodes or to the first and second source regions. 
     
     
       14. The transistor of  claim 12 , wherein the first conductive layer formed in the trench is electrically connected to the first and second gate electrodes to form a trench conductive field plate for the vertical drain current path, the field plate being biased to an accumulation mode when the transistor is turned on to reduce the resistivity of the vertical drain current path. 
     
     
       15. The transistor of  claim 12 , wherein the thin dielectric layer comprises a thin oxide layer, the first conductive layer comprises a polysilicon layer and the second conductive layer comprises one of aluminum or tungsten. 
     
     
       16. The transistor of  claim 12 , wherein the trench is positioned in the drain region and the drain region has a first length between the trench and first gate electrode and a second length between the trench and the second gate electrode, the first length does not equal the second length. 
     
     
       17. The transistor of  claim 12 , wherein the trench is positioned in the drain region and the drain region has a first length between the trench and first gate electrode and a second length between the trench and the second gate electrode, the first length being the same as the second length. 
     
     
       18. The transistor of  claim 12 , wherein the semiconductor body comprises:
 a substrate of the first conductivity type; and 
 an epitaxial layer formed on the substrate and a well region of the first conductivity type formed in the epitaxial layer, 
 wherein the first and second portions of the semiconductor body and the trench are formed in the well region. 
 
     
     
       19. The transistor of  claim 12 , wherein the transistor comprises a double-diffused MOS transistor with a lateral channel under the gate electrode and a vertical drain current path in the doped sidewall region along the sidewall of the trench. 
     
     
       20. The transistor of  claim 12 , wherein the drain region is more heavily doped than the doped sidewall region.