Reference-locked clock generator

Abstract

Clock generation from an external reference by generating a reference clock gating signal using a reference clock gating circuit; enabling a ring-oscillator-injection mode using the reference clock gating signal to disable a first buffer of a ring oscillator and to enable a reference clock injection buffer, the first buffer and the injection buffer having parallel connected outputs that connect to a next buffer input; receiving a reference clock transition of a reference clock signal at the injection buffer and injecting it into the next buffer; and enabling a ring-oscillator-closed-loop mode by using the reference clock gating signal to enable the first buffer and to disable the reference clock injection buffer.

I claim: 
     
       1. A method comprising:
 generating a reference clock gating signal using a reference clock gating circuit; 
 enabling a ring-oscillator-injection mode by using the reference clock gating signal to disable a first buffer of a ring oscillator and to enable a reference clock injection buffer, the first buffer and the injection buffer having parallel connected outputs that connect to a next buffer input of a next buffer of the ring oscillator; and, 
 while in the ring-oscillator-injection mode, receiving a reference clock transition of a reference clock signal at the reference clock injection buffer and injecting it into the next buffer; and, 
 enabling a ring-oscillator-closed-loop mode by using the reference clock gating signal to enable the first buffer and to disable the reference clock injection buffer. 
 
     
     
       2. The method of  claim 1 , wherein generating the reference clock gating signal comprises changing the reference clock gating signal to an enable state prior to an estimated time of the reference clock transition. 
     
     
       3. The method of  claim 2 , further comprising:
 estimating the estimated time of the reference clock transition by counting a number N−1 of ring oscillator cycles after receiving a prior reference clock transition, wherein the ring oscillator operates at a frequency of N times a frequency of the reference clock signal. 
 
     
     
       4. The method of  claim 1 , further comprising:
 configuring the next buffer and one or more additional buffers of the ring oscillator with one or more enable circuits and applying a continuous enable signal to the next buffer and to the one or more additional buffers of the ring oscillator. 
 
     
     
       5. The method of  claim 1 , further comprising:
 generating a ring oscillator error signal; and 
 responsively adjusting a delay value of at least one of the next buffer and one or more additional buffers of the ring oscillator. 
 
     
     
       6. The method of  claim 5 , wherein the adjusted delay value is similar to a delay of the reference clock injection buffer. 
     
     
       7. The method of  claim 5 , wherein generating the ring oscillator error signal is based on the reference clock signal and a ring-oscillator output signal. 
     
     
       8. The method of  claim 7 , wherein generating the ring oscillator error signal comprises:
 comparing a rising edge of the reference clock signal with a rising edge of a frequency-divided version of the ring-oscillator output signal. 
 
     
     
       9. The method of  claim 8 , further comprising selectively adjusting a value of a frequency divisor N used to generate the frequency-divided version of the ring-oscillator output signal according to a frequency of the reference clock signal. 
     
     
       10. An apparatus comprising:
 a voltage controlled oscillator configured to receive a reference clock signal and to generate a system clock signal; the voltage controlled oscillator comprising a buffer chain of buffer circuit blocks, the buffer chain having a chain input and a chain output, the chain of buffer circuit blocks comprising:
 an injection buffer circuit block; and 
 one or more additional buffer circuit blocks, 
 wherein each of the one or more additional buffer circuit blocks comprises a first buffer and a second buffer and wherein the injection buffer circuit block comprises an injection buffer and a delay buffer, wherein the injection buffer has an injection input and is configured to receive the reference clock signal at the injection input; and wherein the delay buffer has an input connected to the chain output of the buffer chain; and wherein the delay buffer circuit and the injection buffer circuit have parallel connected outputs that connect to the chain input of the buffer chain; 
 
 and 
 a selection circuit configured to generate a control signal and to provide the control signal to the injection buffer circuit block; and 
 wherein the injection buffer circuit block is configured to switch between a first mode and a second mode responsively to the control signal from the selection circuit, 
 wherein in the first mode the delay buffer is disabled and the injection buffer is enabled and is configured to provide the reference clock signal to the chain input of the buffer chain, and 
 wherein in the second mode the injection buffer is disabled and the delay buffer is enabled and is connected to the chain input of the buffer chain to form a closed loop with the first buffers of the one or more additional buffer circuit blocks. 
 
     
     
       11. The apparatus of  claim 10  wherein the voltage controlled oscillator comprises the selection circuit. 
     
     
       12. The apparatus of  claim 10  wherein the injection buffer circuit block is configured to receive the control signal from the selection circuit at a selection input and the control signal comprises a first and a second multiplexer control signal. 
     
     
       13. The apparatus of  claim 12  wherein the injection buffer comprises an injection enable circuit configured to receive the first multiplexer control signal and the delay buffer comprises a delay enable circuit configured to receive the second multiplexer control signal. 
     
     
       14. The apparatus of  claim 10  wherein the injection buffer circuit block and the one or more additional buffer circuit blocks are identically configured and wherein the second buffers of the one or more additional buffer circuit blocks are continuously disabled and the first buffers of the one or more additional buffer circuit blocks are continuously enabled. 
     
     
       15. The apparatus of  claim 10  wherein each of the injection buffer and the second buffers of the one or more additional buffer circuit blocks comprises a differential comparator and wherein the injection buffer is configured to receive the reference clock signal at the differential comparator. 
     
     
       16. The apparatus of  claim 10 , further comprising:
 a frequency divider connected to the chain output of the buffer chain and configured to receive a clock signal from the buffer chain and to divide the clock signal to generate a frequency divided clock signal; and 
 an error circuit configured to receive the reference clock signal and the frequency divided clock signal and to generate an error signal at an error circuit output. 
 
     
     
       17. The apparatus of  claim 16 , further comprising:
 a delay adjustment circuit connected to the error circuit output via a low pass filter and configured to adjust a frequency of the clock signal from the buffer chain by providing delay adjustments to one or more buffer circuit blocks of the buffer chain. 
 
     
     
       18. The apparatus of  claim 10 , wherein the selection circuit comprises a reference clock gating circuit, the control signal comprises a reference clock gating signal, and wherein the apparatus further comprises:
 a reference clock circuit configured to generate the reference clock signal and to provide the reference clock signal to the voltage controlled oscillator. 
 
     
     
       19. An apparatus comprising:
 a buffer chain of buffer circuit blocks configured to generate a system clock signal, the buffer chain having a chain input and a chain output, the chain of buffer circuit blocks comprising:
 an injection buffer circuit block comprising an injection buffer enable circuit and a delay buffer enable circuit; and 
 one or more additional buffer circuit blocks, 
 wherein each of the one or more additional buffer circuit blocks comprises at least a first buffer and wherein the injection buffer circuit block comprises an injection buffer and a delay buffer, wherein the injection buffer has an injection input and is configured to receive a reference clock signal at the injection input; and 
 wherein the delay buffer has an input connected to the chain output of the buffer chain; and wherein the delay buffer circuit and the injection buffer circuit have parallel connected outputs that connect to the chain input of the buffer chain; 
 
 and 
 a selection circuit configured to generate a control signal and to provide the control signal to the injection buffer circuit block at one or more of the injection buffer enable circuit and the delay buffer enable circuit; and 
 wherein the injection buffer circuit block is configured to switch between a first mode and a second mode responsively to the control signal from the selection circuit, 
 wherein in the first mode the injection buffer is enabled and is configured to provide the reference clock signal to the chain input of the buffer chain, and 
 wherein in the second mode the delay buffer is enabled and is connected to the chain input of the buffer chain to form a closed loop with the first buffers of the one or more additional buffer circuit blocks. 
 
     
     
       20. An apparatus comprising:
 a buffer chain having a plurality of serially-connected buffer circuits and having a chain input and a chain output; 
 a ring multiplexer having an injection input, a ring input connected to the chain output, a multiplexer output connected to the chain input, and an injection selection input, the injection input configured to receive a reference clock signal, wherein the ring multiplexer comprises (i) an injection buffer; (ii) a last buffer enable circuit of a last buffer circuit of the buffer chain; and (iii) an injection buffer enable circuit of the injection buffer, and wherein the injection selection input is connected to the last buffer enable circuit and the injection buffer enable circuit; and 
 a reference clock gating circuit connected to the injection selection input, the reference clock gating circuit configured to generate a reference clock gating signal on the injection selection input to selectively enable the reference clock signal to be injected into the chain input.