Analog to digital converter device and method for generating testing signal

Abstract

An analog-to-digital converter (ADC) device includes analog-to-digital converter circuitries and a data output circuitry. The ADC circuitries correspond to channels respectively, and convert an input signal to generate quantization outputs according to interleaved clock signals, wherein each of the interleaved clock signals has a sampling frequency. The data output circuitry performs a down-sampling operation according to a first control signal and the quantization outputs, in order to generate a digital signal. The first digital signal is for determining a performance of the ADC circuitries, and a frequency of the digital signal is N/M times of the sampling frequency, and N is a positive integer and is a number of the channels.

What is claimed is: 
     
       1. An analog-to-digital converter device, comprising:
 a plurality of analog-to-digital converter circuitries, corresponding to a plurality of channels respectively, the plurality of analog-to-digital converter circuitries configured to convert an input signal to generate a plurality of quantization outputs according to a plurality of interleaved clock signals, wherein each of the plurality of interleaved clock signals has a sampling frequency; and 
 a data output circuitry coupled to the plurality of analog-to-digital converter circuitries, the data output circuitry configured to perform a down-sampling operation according to a first control signal and the plurality of quantization outputs, in order to generate a first digital signal, 
 wherein the first digital signal is for determining a performance of the plurality of analog-to-digital converter circuitries, and a frequency of the first digital signal is (N/M) times of the sampling frequency, and N is a positive integer and is a number of the plurality of channels. 
 
     
     
       2. The analog-to-digital converter device of  claim 1 , wherein a frequency of the first control signal is N/M times of the sampling frequency. 
     
     
       3. The analog-to-digital converter device of  claim 1 , wherein the data output circuitry comprises:
 a multiplexer coupled to the plurality of analog-to-digital converter circuitries, the multiplexer configured to select an output from the plurality of quantization outputs according to a second control signal, and to output the selected output as a second digital signal; and 
 a down-sampling circuit coupled to the multiplexer, the down-sampling circuit configured to perform the down-sampling operation according to the first control signal and the second digital signal, in order to generate the first digital signal, wherein M is a prime number different from N. 
 
     
     
       4. The analog-to-digital converter device of  claim 3 , wherein a frequency of the second control signal is N times of the sampling frequency. 
     
     
       5. The analog-to-digital converter device of  claim 1 , wherein the data output circuitry comprises:
 a multiplexer coupled to the plurality of analog-to-digital converter circuitries, the multiplexer configured to select an output from the plurality of quantization outputs according to the first control signal, and to output the selected output as a second digital signal; and 
 a sequential circuit coupled to the multiplexer, the sequential circuit configured to combine the second digital signal and at least one redundant data, in order to generate the first digital signal. 
 
     
     
       6. The analog-to-digital converter device of  claim 1 , wherein a frequency of the first control signal is the same as the sampling frequency. 
     
     
       7. The analog-to-digital converter device of  claim 1 , wherein the data output circuitry comprises:
 a first data output sub-circuit coupled to the plurality of analog-to-digital converter circuitries, the first data output sub-circuit configured to perform a data combination operation according to a second control signal and the plurality of quantization outputs to generate a second digital signal, and to perform the down-sampling operation according to the first control signal and the second digital signal, in order to generate a third digital signal; 
 a second data output sub-circuit coupled to the plurality of analog-to-digital converter circuitries, the second data output sub-circuit configured to select an output from the plurality of quantization outputs according to a third control signal, and to output the selected output as a fourth digital signal, and to perform the down-sampling operation according to the fourth digital signal, in order to generate a fifth digital signal; and 
 a control circuit coupled to the first data output sub-circuit and the second data output sub-circuit, the control circuit configured to selectively output one of the third digital signal and the fifth digital signal as the first digital signal. 
 
     
     
       8. The analog-to-digital converter device of  claim 7 , wherein the control circuit comprises:
 a first switch coupled to the first data output sub-circuit to receive the third digital signal, wherein if the first switch is turned on, the first data output sub-circuit outputs the third digital signal, via the first switch, as the first digital signal; and 
 a second switch coupled to the second data output sub-circuit to receive the fifth digital signal, wherein if the second switch is turned on, the second data output sub-circuit outputs the fifth digital signal, via the second switch, as the first digital signal. 
 
     
     
       9. A method for generating testing signal, the method comprising:
 converting, by a plurality of analog-to-digital converter circuitries that correspond to a plurality of channels respectively, an input signal according to a plurality of interleaved clock signals to generate a plurality of quantization outputs, wherein each of the plurality of interleaved clock signals has a sampling frequency; and 
 performing a down-sampling operation according to a first control signal and the plurality of quantization outputs, in order to output a first digital signal, 
 wherein the first digital signal is for determining a performance of the plurality of analog-to-digital converter circuitries, a frequency of the first digital signal is N/M times of the sampling frequency, and N is a positive integer and is a number of the plurality of channels. 
 
     
     
       10. The method of  claim 9 , wherein a frequency of the first control signal is N/M times of the sampling frequency. 
     
     
       11. The method of  claim 9 , wherein performing the down-sampling operation comprises:
 selecting, by a multiplexer, an output from the plurality of quantization outputs according to a second control signal, in order to output the selected output as a second digital signal; and 
 performing, by a down-sampling circuit, the down-sampling operation according to the first control signal and the second digital signal, in order to generate the first digital signal, wherein M is a prime number different from N. 
 
     
     
       12. The method of  claim 11 , wherein a frequency of the second control signal is N times of the sampling frequency. 
     
     
       13. The method of  claim 9 , wherein performing the down-sampling operation comprises:
 selecting, by a multiplexer, an output from the plurality of quantization outputs according to the first control signal, in order output the selected output as a second digital signal; and 
 combining, by a sequential circuit, the second digital signal and at least one redundant data, in order to generate the first digital signal. 
 
     
     
       14. The method of  claim 13 , wherein a frequency of the first control signal is the same as the sampling frequency. 
     
     
       15. The method of  claim 9 , wherein performing the down-sampling operation comprises:
 performing, by a first data output sub-circuit, a data combination operation according to a second control signal and the plurality of quantization outputs to generate a second digital signal, and performing the down-sampling operation according to the first control signal and the second digital signal, in order to generate a third digital signal; 
 selecting, by a second data output sub-circuit, an output from the plurality of quantization outputs according to a third control signal, to output the selected output as a fourth digital signal, and performing the down-sampling operation according to the fourth digital signal, in order to generate a fifth digital signal; and 
 selectively outputting one of the third digital signal and the fifth digital signal as the first digital signal. 
 
     
     
       16. The method of  claim 15 , wherein selectively outputting the one of the third digital signal and the fifth digital signal as the first digital signal comprises:
 turning on a first switch, wherein if the first switch is turned on, the first data output sub-circuit outputs the third digital signal, via the first switch, as the first digital signal; and 
 turning on a second switch, wherein if the second switch is turned on, the second data output sub-circuit outputs the fifth digital signal, via the second switch, as the first digital signal.