Bias boosting circuit for amplifier

Abstract

An amplification system can include a bias booster circuit and an amplifier that amplifies an input signal to drive a load. The bias boosting circuit can include a negative bias booster that applies a charge to an input node of the amplifier in response to a negative half-cycle of the input signal that exceeds a boost threshold level. The bias boosting circuit can also include a positive bias booster that discharges the input node of the amplifier during a positive half-cycle of the input signal that exceeds the boost threshold level. The discharging by the positive bias booster is slower than the charging by the negative bias booster to induce a bias voltage increase from a quiescent bias voltage on the input node of the amplifier.

What is claimed is: 
     
       1. An amplification system comprising:
 an amplifier comprising a field effect transistor (FET) that amplifies an input signal to drive a load and an amplifier transistor; and 
 a bias boosting circuit comprising:
 a negative bias booster that applies a charge to an input node of the amplifier in response to a negative half-cycle of the input signal that exceeds a boost threshold level, wherein the negative bias booster includes a negative bias boost transistor; 
 a positive bias booster that discharges the input node of the amplifier during a positive half-cycle of the input signal that exceeds the boost threshold level, wherein the discharging by the positive bias booster is slower than the charging by the negative bias booster to induce a bias voltage increase from a quiescent bias voltage on the input node of the amplifier, wherein the positive bias booster includes a positive bias boost transistor; 
 a biasing node that couples the negative bias booster and the positive bias booster; 
 an impedance block that couples the biasing node to the input node, wherein the impedance block comprising a resistive component and an inductive component; and 
 wherein a channel width of the negative bias boost transistor and a channel width of the positive bias boost transistor are smaller than a channel width of the amplifying transistor and a source impedance of the negative bias boost transistor is smaller than a drain impedance of the positive bias boost transistor. 
 
 
     
     
       2. The amplification system of  claim 1 , wherein the FET of the amplifier is connected in a common-source configuration and a gate of the field effect transistor is coupled to the input node of the amplifier. 
     
     
       3. The amplification system of  claim 1 , wherein the FET of the amplifier is a given FET and wherein the amplifier comprises:
 a plurality of field effect transistors (FETs), the given FET being one of the plurality of FETS, wherein a gate of each of the plurality of FETs is coupled to the input node of the amplifier. 
 
     
     
       4. The amplification system of  claim 1 , wherein the negative bias boost transistor comprises:
 a given gallium nitride high electron mobility transistor (HEMT), wherein a source of the given HEMT is coupled to the biasing node, a drain of the given HEMT is coupled to a positive voltage source and a gate of the given HEMT is coupled to a negative voltage source, wherein the negative-half cycle of the input signal causes the given HEMT to transition to operate in the saturated mode, and the positive half-cycle of the input signal causes the given HEMT to operate in the cutoff mode. 
 
     
     
       5. The amplification system of  claim 4 , wherein the positive bias boost transistor comprises:
 another HEMT, wherein a drain of the other HEMT is coupled to the biasing node, a source of the other HEMT is coupled to a second negative voltage source and a gate of the other HEMT is coupled to a third negative voltage source, wherein the negative-half cycle of the input signal causes the other HEMT to operate in the cutoff mode, and the positive half-cycle of the input signal allows the discharge of the charge at the input node of the amplifier through the drain of the other HEMT to the source of the other HEMT. 
 
     
     
       6. The amplification system of  claim 1 , further comprising a diode-compensation circuit coupled to the input node of the amplifier that limits a drop of the bias voltage on the input node of the amplifier. 
     
     
       7. The amplification system of  claim 6 , wherein the diode-compensation circuit comprises a gallium nitride high electron mobility transistor (HEMT), wherein a drain and a source of the HEMT are coupled to the input node of the transistor. 
     
     
       8. The amplification system of  claim 7 , wherein a negative bias voltage is applied to a gate of the HEMT. 
     
     
       9. The amplification system of  claim 1 , wherein the load comprises a transmission line of a radio frequency (RF) antenna. 
     
     
       10. An integrated circuit (IC) chip comprising:
 an amplifier comprising a plurality of field effect transistors (FETs) that amplify an input signal to drive a load; and 
 a bias boosting circuit comprising:
 a negative bias booster that applies a charge to each gate of the plurality of FETs of the amplifier in response to a negative half-cycle of the input signal that exceeds a boost threshold level and includes a negative bias boost transistor; 
 a positive bias booster that includes a positive bias boost transistor and discharges an input node of each gate of the plurality of FETs of the amplifier during a positive half-cycle of the input signal that exceeds the boost threshold level, wherein the discharging by the positive bias booster is slower than the charging by the negative bias booster to induce a bias voltage increase from a quiescent bias voltage on each gate of the plurality of FETs; 
 a biasing node that couples the negative bias booster and the positive bias booster; 
 an impedance block that couples the biasing node to the input node, wherein the impedance block comprising a resistive component and an inductive component; and 
 wherein a channel width of the negative bias boost transistor and a channel width of the positive bias boost transistor are smaller than a channel width of each of the plurality of FETs of the amplifier and a source impedance of the negative bias boost transistor is smaller than a drain impedance of the positive bias boost transistor. 
 
 
     
     
       11. The IC chip of  claim 10 , further comprising:
 a diode compensation circuit that limits a voltage drop of each gate of the plurality of FETs. 
 
     
     
       12. The IC chip of  claim 10 , wherein the inductive component of the impedance block comprises an inductor. 
     
     
       13. The IC chip of  claim 10 , wherein the impedance block sets the bias voltage for the gate of each of the plurality of FETs. 
     
     
       14. The IC chip of  claim 10 ,
 wherein the negative bias boost transistor comprises a given gallium nitride high electron mobility transistor (HEMT), wherein a source of the given HEMT is coupled to the biasing node, a drain of the given HEMT is coupled to a positive voltage source and a gate of the given HEMT is coupled to a first negative voltage source, wherein the negative-half cycle of the input signal causes the given HEMT to transition to operate in the saturated mode, and the positive half-cycle of the input signal causes the given HEMT to operate in the cutoff mode; and 
 wherein the positive bias boost transistor comprises another HEMT, wherein a drain of the other HEMT is coupled to the biasing node, a source of the other HEMT is coupled to a second negative voltage source and a gate of the other HEMT is coupled to a third negative voltage source, wherein the negative-half cycle of the input signal causes the other HEMT to operate in the cutoff mode, and the positive half-cycle of the input signal allows the discharge of the charge at each gate of the plurality of FETs through the drain of the other HEMT to the source of the other HEMT. 
 
     
     
       15. The IC chip of  claim 14 , wherein the given HEMT and the other HEMT of the bias boosting circuit are smaller than the plurality of FETs of the amplifier. 
     
     
       16. The IC chip of  claim 10 , wherein the bias voltage improves the linearity and power-added efficiency (PAE) of the amplifier by increasing a one decibel compression point of the amplifier. 
     
     
       17. An amplification system comprising:
 an amplifier comprising a field effect transistor (FET) that amplifies an input signal to drive a load; 
 a bias boosting circuit that accumulates a charge at a gate of the FET of the amplifier in response to multiple cycles of an input signal that exceeds a boost threshold level to induce a bias voltage increase from a quiescent bias voltage on the gate of the amplifier, wherein the bias boosting circuit includes a positive bias boost transistor and a negative bias boost transistor such that a channel width of the negative bias boost transistor and a channel width of the positive bias boost transistor are smaller than a channel width of the FET of the amplifier; 
 a diode-compensation circuit that limits a voltage drop at the gate of the FET to a predetermined level; 
 a biasing node that couples the negative bias booster and the positive bias booster; 
 an impedance block that couples the biasing node to an input node, wherein the impedance block comprising a resistive component and an inductive component; and 
 wherein a source impedance of the negative bias boost transistor is smaller than a drain impedance of the positive bias boost transistor. 
 
     
     
       18. The amplification system of  claim 17 , wherein the bias boosting circuit discharges the charge at the gate of the FET a slower rate than the bias boosting circuit applies the charge to the gate of the FET to accumulate the charge.