OLED pixel circuit and method for retarding aging of OLED device

Abstract

The present disclosure provides an OLED pixel circuit and a method for retarding the aging of an OLED device. By providing a first sub-pixel driving unit, a second sub-pixel driving unit, a first reverse biasing unit, and a second reverse biasing unit and by simple control timing, a first light emitting diode and a second light emitting diode will not always be in a DC biased state, and the first light emitting diode and the second light emitting diode will emit light alternately in different frames.

What is claimed is: 
     
       1. An OLED pixel circuit, comprising:
 a first sub-pixel driving unit, comprising a first thin-film transistor, a fifth thin-film transistor, a first capacitor, and a first light emitting diode; 
 a second sub-pixel driving unit, comprising a second thin-film transistor, a sixth thin-film transistor, a second capacitor, and a second light emitting diode, wherein: 
 both a source of the first thin-film transistor and a source of the second thin-film transistor are connected to a positive supply voltage; a gate of the first thin-film transistor is electrically connected to a first node, and a gate of the second thin-film transistor is electrically connected to a second node; and, a drain of the first thin-film transistor is electrically connected to an anode of the first light emitting diode, and a drain of the second thin-film transistor is electrically connected to an anode of the second light emitting diode; 
 a data signal is fed into both a source of the fifth thin-film transistor and a source of the sixth thin-film transistor; a drain of the fifth thin-film transistor is electrically connected to the first node, and a drain of the sixth thin-film transistor is electrically connected to the second node; and, a second control signal is fed into a gate of the fifth thin-film transistor, and a third control signal is fed into a gate of the sixth thin-film transistor; and 
 one end of the first capacitor is electrically connected to the first node, while the other end thereof is connected to the positive supply voltage; and, one end of the second capacitor is electrically connected to the second node, while the other end thereof is connected to the positive supply voltage; 
 a first reverse biasing unit, comprising a third thin-film transistor, a seventh thin-film transistor, and a ninth thin-film transistor; and 
 a second reverse biasing unit, comprising a fourth thin-film transistor, an eighth thin-film transistor, and a tenth thin-film transistor, wherein: 
 a first control signal is fed into both a gate of the third thin-film transistor and a gate of the fourth thin-film transistor; both a source of the third thin-film transistor and a source of the fourth thin-film transistor are connected to the positive supply voltage; and, a drain of the third thin-film transistor is electrically connected to a cathode of the first light emitting diode, and a drain of the fourth thin-film transistor is electrically connected to a cathode of the second light emitting diode; 
 the first control signal is fed into both a gate of the seventh thin-film transistor and a gate of the eighth thin-film transistor; a drain of the seventh thin-film transistor is electrically connected to an anode terminal of the first light emitting diode, and a drain of the eighth thin-film transistor is electrically connected to an anode terminal of the second light emitting diode; and, both a source of the seventh thin-film transistor and a source of the eighth thin-film transistor are connected to a negative supply voltage; 
 the first control signal is fed into both a gate of the ninth thin-film transistor and a gate of the tenth thin-film transistor; both a source of the ninth thin-film transistor and a source of the tenth thin-film transistor are connected to the negative supply voltage; and, a drain of the ninth thin-film transistor is electrically connected to the cathode of the first light emitting diode, and a drain of the tenth thin-film transistor is electrically connected to the cathode of the second light emitting diode; 
 the first control signal, the second control signal, and the third control signal are all provided by an external timing controller; 
 the first thin-film transistor, the second thin-film transistor, the third thin-film transistor, the fourth thin-film transistor, the fifth thin-film transistor, the sixth thin-film transistor, the seventh thin-film transistor, the eighth thin-film transistor, the ninth thin-film transistor, and the tenth thin-film transistor are all low temperature polysilicon thin-film transistors, oxide semiconductor thin-film transistors or amorphous silicon thin-film transistors; wherein 
 the first thin-film transistor, the second thin-film transistor, the third thin-film transistor, the fifth thin-film transistor, the sixth thin-film transistor, the seventh thin-film transistor, and the tenth thin-film transistor are all N-type thin-film transistors; the fourth thin-film transistor, the eighth thin-film transistor, and the ninth thin-film transistor are all P-type thin-film transistors; 
 in the potential storage stage of the first light emitting diode, the first control signal provides a low potential, the second control signal provides a high potential, and the third control signal provides a low potential; 
 in the luminescent display stage of the first light emitting diode, the first control signal provides a low potential, the second control signal provides a low potential, and the third control signal provides a low potential; 
 in the potential storage stage of the second light emitting diode, the first control signal provides a high potential, the second control signal provides a low potential, and the third control signal provides a high potential; and 
 in the luminescent display stage of the second light emitting diode, the first control signal provides a high potential, the second control signal provides a low potential, and the third control signal provides a low potential. 
 
     
     
       2. The OLED pixel circuit as claimed in  claim 1 , wherein the first control signal, the second control signal, and the third control signal are combined to sequentially correspond to a potential storage stage of the first light emitting diode, a luminescent display stage of the first light emitting diode, a potential storage stage of the second light emitting diode and a luminescent display stage of the second light emitting diode. 
     
     
       3. A method for retarding aging of an OLED device, comprising the following steps:
 step  1 : providing the OLED pixel circuit according to  claim 1 ; 
 step  2 : entering a potential storage stage of the first light emitting diode, the potential storage stage of the first light emitting diode being in an Nth frame; 
 controlling, by the first control signal, the second control signal, and the third control signal, to turn on the fourth thin-film transistor, the fifth thin-film transistor, the eighth thin-film transistor, and the ninth thin-film transistor and to turn off the first thin-film transistor, the second thin-film transistor, the third thin-film transistor, the sixth thin-film transistor, the seventh thin-film transistor, and the tenth thin-film transistor, storing a potential of a data signal by the first capacitor, and bringing the second light emitting diode into a reversely biased state; 
 step  3 : entering a luminescent display stage of the first light emitting diode, the luminescent display stage of the first light emitting diode being in an Nth frame; 
 controlling, by the first control signal, the second control signal, and the third control signal, to turn on the first thin-film transistor, the fourth thin-film transistor, the eighth thin-film transistor, and the ninth thin-film transistor and to turn off the second thin-film transistor, the third thin-film transistor, the fifth thin-film transistor, the sixth thin-film transistor, the seventh thin-film transistor, and the tenth thin-film transistor, emitting light by the first light emitting diode, and keeping the second light emitting diode in the reversely biased state; 
 step  4 : entering a potential storage stage of the second light emitting diode, the potential storage stage of the second light emitting diode being in an (N+1)th frame; 
 controlling, by the first control signal, the second control signal, and the third control signal, to turn on the first thin-film transistor, the second thin-film transistor, the third thin-film transistor, the sixth thin-film transistor, the seventh thin-film transistor, and the ninth thin-film transistor and to turn off the fourth thin-film transistor, the fifth thin-film transistor, the eighth thin-film transistor, and the tenth thin-film transistor, storing a potential of a data signal by the second capacitor, and bringing the first light emitting diode into the reversely biased state; and 
 step  5 : entering a luminescent display stage of the second light emitting diode, the luminescent display stage of the second light emitting diode being in an (N+1)th frame; 
 controlling, by the first control signal, the second control signal, and the third control signal, to turn on the second thin-film transistor, the third thin-film transistor, the seventh thin-film transistor, and the tenth thin-film transistor and to turn off the first thin-film transistor, the fourth thin-film transistor, the fifth thin-film transistor, the sixth thin-film transistor, the eighth thin-film transistor, and the ninth thin-film transistor, emitting light by the second light emitting diode, and keeping the first light emitting diode in the reversely biased state; wherein 
 the first thin-film transistor, the second thin-film transistor, the third thin-film transistor, the fifth thin-film transistor, the sixth thin-film transistor, the seventh thin-film transistor, and the tenth thin-film transistor are all N-type thin-film transistors; the fourth thin-film transistor, the eighth thin-film transistor, and the ninth thin-film transistor are all P-type thin-film transistors; 
 in the potential storage stage of the first light emitting diode, the first control signal provides a low potential, the second control signal provides a high potential, and the third control signal provides a low potential; 
 in the luminescent display stage of the first light emitting diode, the first control signal provides a low potential, the second control signal provides a low potential, and the third control signal provides a low potential; 
 in the potential storage stage of the second light emitting diode, the first control signal provides a high potential, the second control signal provides a low potential, and the third control signal provides a high potential; and 
 in the luminescent display stage of the second light emitting diode, the first control signal provides a high potential, the second control signal provides a low potential, and the third control signal provides a low potential. 
 
     
     
       4. The method for retarding aging of an OLED device as claimed in  claim 3 , wherein the first control signal, the second control signal, and the third control signal are all provided by an external timing controller. 
     
     
       5. The method for retarding aging of an OLED device as claimed in  claim 3 , wherein the first thin-film transistor, the second thin-film transistor, the third thin-film transistor, the fourth thin-film transistor, the fifth thin-film transistor, the sixth thin-film transistor, the seventh thin-film transistor, the eighth thin-film transistor, the ninth thin-film transistor, and the tenth thin-film transistor are all low temperature polysilicon thin-film transistors, oxide semiconductor thin-film transistors or amorphous silicon thin-film transistors. 
     
     
       6. An OLED pixel circuit, comprising:
 a first sub-pixel driving unit, comprising a first thin-film transistor, a fifth thin-film transistor, a first capacitor, and a first light emitting diode; 
 a second sub-pixel driving unit, comprising a second thin-film transistor, a sixth thin-film transistor, a second capacitor, and a second light emitting diode, wherein: 
 both a source of the first thin-film transistor and a source of the second thin-film transistor are connected to a positive supply voltage; a gate of the first thin-film transistor is electrically connected to a first node, and a gate of the second thin-film transistor is electrically connected to a second node; and, a drain of the first thin-film transistor is electrically connected to an anode of the first light emitting diode, and a drain of the second thin-film transistor is electrically connected to an anode of the second light emitting diode; 
 a data signal is fed into both a source of the fifth thin-film transistor and a source of the sixth thin-film transistor; a drain of the fifth thin-film transistor is electrically connected to the first node, and a drain of the sixth thin-film transistor is electrically connected to the second node; and, a second control signal is fed into a gate of the fifth thin-film transistor, and a third control signal is fed into a gate of the sixth thin-film transistor; and 
 one end of the first capacitor is electrically connected to the first node, while the other end thereof is connected to the positive supply voltage; and, one end of the second capacitor is electrically connected to the second node, while the other end thereof is connected to the positive supply voltage; 
 a first reverse biasing unit, comprising a third thin-film transistor, a seventh thin-film transistor, and a ninth thin-film transistor; and 
 a second reverse biasing unit, comprising a fourth thin-film transistor, an eighth thin-film transistor, and a tenth thin-film transistor, wherein: 
 a first control signal is fed into both a gate of the third thin-film transistor and a gate of the fourth thin-film transistor; both a source of the third thin-film transistor and a source of the fourth thin-film transistor are connected to the positive supply voltage; and, a drain of the third thin-film transistor is electrically connected to a cathode of the first light emitting diode, and a drain of the fourth thin-film transistor is electrically connected to a cathode of the second light emitting diode; 
 the first control signal is fed into both a gate of the seventh thin-film transistor and a gate of the eighth thin-film transistor; a drain of the seventh thin-film transistor is electrically connected to an anode terminal of the first light emitting diode, and a drain of the eighth thin-film transistor is electrically connected to an anode terminal of the second light emitting diode; and, both a source of the seventh thin-film transistor and a source of the eighth thin-film transistor are connected to a negative supply voltage; 
 the first control signal is fed into both a gate of the ninth thin-film transistor and a gate of the tenth thin-film transistor; both a source of the ninth thin-film transistor and a source of the tenth thin-film transistor are connected to the negative supply voltage; and, a drain of the ninth thin-film transistor is electrically connected to the cathode of the first light emitting diode, and a drain of the tenth thin-film transistor is electrically connected to the cathode of the second light emitting diode; wherein 
 the first thin-film transistor, the second thin-film transistor, the third thin-film transistor, the fifth thin-film transistor, the sixth thin-film transistor, the seventh thin-film transistor, and the tenth thin-film transistor are all N-type thin-film transistors; the fourth thin-film transistor, the eighth thin-film transistor, and the ninth thin-film transistor are all P-type thin-film transistors; 
 in the potential storage stage of the first light emitting diode, the first control signal provides a low potential, the second control signal provides a high potential, and the third control signal provides a low potential; 
 in the luminescent display stage of the first light emitting diode, the first control signal provides a low potential, the second control signal provides a low potential, and the third control signal provides a low potential; 
 in the potential storage stage of the second light emitting diode, the first control signal provides a high potential, the second control signal provides a low potential, and the third control signal provides a high potential; and 
 in the luminescent display stage of the second light emitting diode, the first control signal provides a high potential, the second control signal provides a low potential, and the third control signal provides a low potential. 
 
     
     
       7. The OLED pixel circuit as claimed in  claim 6 , wherein the first control signal, the second control signal, and the third control signal are all provided by an external timing controller. 
     
     
       8. The OLED pixel circuit as claimed in  claim 6 , wherein the first thin-film transistor, the second thin-film transistor, the third thin-film transistor, the fourth thin-film transistor, the fifth thin-film transistor, the sixth thin-film transistor, the seventh thin-film transistor, the eighth thin-film transistor, the ninth thin-film transistor, and the tenth thin-film transistor are all low temperature polysilicon thin-film transistors, oxide semiconductor thin-film transistors or amorphous silicon thin-film transistors. 
     
     
       9. The OLED pixel circuit as claimed in  claim 6 , wherein the first control signal, the second control signal, and the third control signal are combined to sequentially correspond to a potential storage stage of the first light emitting diode, a luminescent display stage of the first light emitting diode, a potential storage stage of the second light emitting diode and a luminescent display stage of the second light emitting diode.