Memory device and method of manufacturing the same

Abstract

A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.

What is claimed is: 
     
       1. A memory device, comprising:
 a substrate; 
 an insulating interlayer disposed on the substrate; 
 a word line disposed on the insulation interlayer; 
 a bottom electrode disposed on the word line; 
 a selection device disposed on the bottom electrode, wherein a first capping layer is disposed on a side wall of the selection device, wherein an outer sidewall of the first capping layer is coplanar with an outer sidewall of the word line along a direction orthogonal to an upper surface of the substrate; 
 a middle electrode disposed on the selection device; 
 a variable resistance layer disposed on the middle electrode, wherein a second capping layer is disposed on a side wall of the variable resistance layer; 
 a top electrode disposed on the variable resistance layer; and 
 a bit line disposed on the top electrode. 
 
     
     
       2. The memory device of  claim 1 , wherein the first capping layer has a first thickness in a first direction substantially parallel to a top surface of the substrate, the second capping layer has a second thickness in the first direction, and the second thickness is substantially greater than the first thickness. 
     
     
       3. The memory device of  claim 1 , wherein the selection device has a first width in a first direction substantially parallel to a top surface of the substrate, the variable resistance layer has a second width in the first direction, and the second width is substantially smaller than the first width. 
     
     
       4. The memory device of  claim 3 , wherein the word line has a third width in the first direction,
 wherein the third width is substantially greater than the first width or the second width. 
 
     
     
       5. The memory device of  claim 1 , further comprising an insulation pattern disposed on side walls of each of the first capping layer, the middle electrode, and the second capping layer, wherein the insulation pattern is separated from the side wall of the selection device by the first capping layer, and wherein the insulation pattern is separated from the side wall of the variable resistance layer by the second capping layer. 
     
     
       6. The memory device of  claim 1 , further comprising an insulation liner between the second capping layer and the variable resistance layer. 
     
     
       7. The memory device of  claim 1 , wherein a side wall of the word line is substantially aligned with a side wall of the first capping layer. 
     
     
       8. A memory device, comprising:
 a substrate; 
 an insulating interlayer disposed on the substrate; 
 a word line disposed on the insulation interlayer; 
 a bottom electrode disposed on the word line; 
 a selection device disposed on the bottom electrode, wherein a first capping layer is disposed on a side wall of the selection device; 
 a middle electrode disposed on the selection device; 
 a variable resistance layer disposed on the middle electrode, wherein a second capping layer is disposed on a side wall of the variable resistance layer, and wherein the second capping layer is unconnected with the first capping layer; 
 a top electrode disposed on the variable resistance layer; and 
 a bit line disposed on the top electrode, 
 wherein the selection device has a first width in a first direction parallel to a top surface of the substrate, the first width is substantially smaller than a width of the word line or a width of the bit line, or 
 wherein the variable resistance layer has a second width in the first direction, the second width is substantially smaller than the width of the word line or the width of the bit line. 
 
     
     
       9. The memory device of  claim 8 , wherein the second width is substantially smaller than the first width. 
     
     
       10. The memory device of  claim 8 , wherein the first capping layer has a first thickness in the first direction, the second capping layer has a second thickness in the first direction, and the second thickness is substantially greater than the first thickness. 
     
     
       11. The memory device of  claim 8 , further comprising an insulation pattern disposed on side walls of each of the first capping layer, the middle electrode, and the second capping layer, wherein the insulation pattern is separated from the side wall of the selection device by the first capping layer, and wherein the insulation pattern is separated from the side wall of the variable resistance layer by the second capping layer. 
     
     
       12. The memory device of  claim 8 , further comprising an insulation liner between the second capping layer and the variable resistance layer. 
     
     
       13. The memory device of  claim 8 , wherein a side wall of the word line is substantially aligned with a side wall of the first capping layer. 
     
     
       14. A memory device, comprising:
 a substrate; 
 an insulating interlayer disposed on the substrate; 
 a word line disposed on the insulation interlayer; 
 a bottom electrode disposed on the word line; 
 a selection device disposed on the bottom electrode, wherein a first capping layer is disposed on a side wall of the selection device, wherein an outer sidewall of the first capping layer is coplanar with an outer sidewall of the word line along a direction orthogonal to an upper surface of the substrate; 
 a middle electrode disposed on the selection device; 
 a variable resistance layer disposed on the middle electrode, wherein a second capping layer is disposed on a side wall of the variable resistance layer; 
 a top electrode disposed on the variable resistance layer; and 
 a bit line disposed on the top electrode, 
 wherein the first capping layer has a first thickness in a first direction substantially parallel to a top surface of the substrate, the second capping layer has a second thickness in the first direction, and the second thickness is different from the first thickness. 
 
     
     
       15. The memory device of  claim 14 , wherein the second thickness is substantially greater than the first thickness. 
     
     
       16. The memory device of  claim 14 , wherein the selection device has a first width in the first direction, the variable resistance layer has a second width in the first direction, and the second width is substantially smaller than the first width. 
     
     
       17. The memory device of  claim 16 , wherein the word line has a third width in the first direction, and the third width is substantially greater than the first width or the second width. 
     
     
       18. The memory device of  claim 14 , wherein a side wall of the word line is substantially aligned with a side wall of the first capping layer.