Electronic apparatus, VLIW processor and control methods for updating a multi-cycle no operation (NOP) instruction

Abstract

An electronic apparatus generating compiled data used in a very long instruction word (VLIW) processor including a plurality of function units is provided. The electronic apparatus includes a storage and a processor configured to control the storage to store the compiled data in which a plurality of VLIW instructions are compiled, identify a VLIW instruction from the compiled data; and update, if a multi-cycle no operation (nop) instruction for the plurality of function units is identified within a cycle corresponding to a latency of the identified VLIW instruction and if an end cycle of another VLIW instruction is within the cycle corresponding to the latency of the identified VLIW instruction, the compiled data by including information on a cycle difference between an end cycle of the identified VLIW instruction and the end cycle of the another VLIW instruction in the multi-cycle nop instruction.

What is claimed is: 
     
       1. An electronic apparatus generating compiled data used in a very long instruction word (VLIW) processor including a plurality of function units, the electronic apparatus comprising:
 a storage; and 
 a processor configured to:
 control the storage to store the compiled data in which a plurality of VLIW instructions are compiled, 
 identify a VLIW instruction from the compiled data, and 
 update, if a multi-cycle no operation (nop) instruction for the plurality of function units is identified within a cycle corresponding to a latency of the identified VLIW instruction and if an end cycle of another VLIW instruction is within the cycle corresponding to the latency of the identified VLIW instruction, the compiled data by including information on a cycle difference between an end cycle of the identified VLIW instruction and the end cycle of the another VLIW instruction in the multi-cycle nop instruction. 
 
 
     
     
       2. The electronic apparatus as claimed in  claim 1 , wherein the another VLIW instruction is an instruction included a cycle in which the identified VLIW instruction is included or a previous cycle thereof. 
     
     
       3. The electronic apparatus as claimed in  claim 1 , wherein the processor synchronizes, if the multi-cycle nop instruction is identified within the cycle corresponding to the latency of the identified VLIW instruction, identification information of the identified VLIW instruction and identification information of the multi-cycle nop instruction included in the compiled data. 
     
     
       4. The electronic apparatus as claimed in  claim 1 , wherein, when updating the compiled data, the processor counts a number of cycles corresponding to the cycle difference between the end cycle of the identified VLIW instruction and the end cycle of the another VLIW instruction and includes the counted value in an operation (OP) code of the multi-cycle nop instruction of the compiled data. 
     
     
       5. The electronic apparatus as claimed in  claim 1 , wherein the processor updates, if at least one VLIW instruction is not identified in the cycles between the end cycle of the another VLIW instruction and the end cycle of the identified VLIW instruction, the compiled data by including the information on the cycle difference in the multi-cycle nop instruction. 
     
     
       6. A very long instruction word (VLIW) processor, comprising:
 a memory; and 
 a plurality of function units, 
 wherein the VLIW processor is configured to:
 control the memory to store compiled data, 
 control the plurality of function units to process the compiled data, 
 sequentially execute at least one VLIW instruction based on the compiled data and 
 shorten, if the at least one VLIW instruction being executed is a predetermined instruction, if an operand of the at least one VLIW instruction comprises a predetermined value, and if a multi-cycle no operation (nop) instruction synchronized with the at least one VLIW instruction is identified within a cycle corresponding to a latency of the at least one VLIW instruction, a cycle of the multi-cycle nop instruction based on information included in the multi-cycle nop instruction. 
 
 
     
     
       7. The VLIW processor as claimed in  claim 6 , wherein the VLIW processor shortens, if a plurality of multi-cycle nop instructions synchronized with the at least one VLIW instruction are identified within the cycle corresponding to the latency of the VLIW instruction, the cycle of the multi-cycle nop instruction with a minimum cycle difference based on information included in the multi-cycle nop instruction. 
     
     
       8. The VLIW processor as claimed in  claim 6 , wherein the VLIW processor is configured to:
 change the latency of the at least one VLIW instruction, if the at least one VLIW instruction being executed is the predetermined VLIW instruction and the operand of the at least one VLIW instruction comprises the predetermined value, and 
 process the at least one VLIW instruction during the changed latency. 
 
     
     
       9. The VLIW processor as claimed in  claim 8 , wherein the VLIW processor shortens, if the multi-cycle no operation (nop) instruction for the plurality of function units is identified within the cycle corresponding to the latency of the at least one VLIW instruction and an end cycle of another VLIW instruction which is being currently executed is within the cycle corresponding to the latency of the at least one VLIW instruction, a cycle of the multi-cycle nop instruction based on a cycle difference between the end cycle of the at least one VLIW instruction and the another VLIW cycle. 
     
     
       10. The VLIW processor as claimed in  claim 9 , further comprising a register,
 wherein the another VLIW instruction comprises the most cycles remaining until an execution completion among VLIW instructions which are being currently executed, and 
 the VLIW processor configured to: 
 store information on the latency of the another VLIW instruction in the register, and 
 shorten, if the end cycle of the another VLIW instruction is within the cycle corresponding to the latency of the at least one VLIW instruction based on the information stored in the register, the cycle of the multi-cycle nop instruction based on the cycle difference. 
 
     
     
       11. The VLIW processor as claimed in  claim 10 , wherein the information on the latency of the another VLIW instruction stored in the register includes at least one of cycle identification information corresponding to the latency of the another VLIW instruction and information on cycles remaining until an execution completion of the another VLIW instruction based on a current cycle. 
     
     
       12. The VLIW processor as claimed in  claim 9 , wherein the VLIW processor shortens, if at least one VLIW instruction is not identified in the cycles between the end cycle of the another VLIW instruction and the end cycle of the at least one VLIW instruction, the cycle of the multi-cycle nop instruction based on the information on the cycle difference. 
     
     
       13. A control method of a very long instruction word (VLIW) processor, the control method comprising:
 sequentially executing at least one VLIW instruction based on compiled data; 
 changing a latency of the at least one VLIW instruction, if the at least one VLIW instruction being executed is a predetermined VLIW instruction and an operand of the at least one VLIW instruction comprises a predetermined value; 
 processing the at least one VLIW instruction during the changed latency; and 
 shortening, if a multi-cycle no operation (nop) instruction for the plurality of function units is identified within the cycle corresponding to the latency of the at least one VLIW instruction and an end cycle of another VLIW instruction which is being currently executed is within the cycle corresponding to the latency of the at least one VLIW instruction, a cycle of the multi-cycle nop instruction based on a cycle difference between the end cycle of the at least one VLIW instruction and the another VLIW cycle. 
 
     
     
       14. The control method as claimed in  claim 13 , wherein the VLIW processor comprises a register,
 wherein the another VLIW instruction comprises the most cycles remaining until an execution completion among VLIW instructions which are being currently executed, and 
 further comprising: 
 storing information on the latency of the another VLIW instruction in the register, and 
 shortening, if the end cycle of the another VLIW instruction is within the cycle corresponding to the latency of the at least one VLIW instruction based on the information stored in the register, the cycle of the multi-cycle nop instruction based on the cycle difference. 
 
     
     
       15. The control method as claimed in  claim 14 , wherein the information on the latency of the another VLIW instruction stored in the register includes at least one of cycle identification information corresponding to the latency of the another VLIW instruction and information on cycles remaining until an execution completion of the another VLIW instruction based on a current cycle. 
     
     
       16. The control method as claimed in  claim 13 , further comprising:
 shortening, if at least one VLIW instruction is not identified in the cycles between the end cycle of the another VLIW instruction and the end cycle of the at least one VLIW instruction, the cycle of the multi-cycle nop instruction based on the information on the cycle difference.