US10381279B2ActiveUtilityA1

Method of manufacturing semiconductor device and semiconductor device

53
Assignee: RENESAS ELECTRONICS CORPPriority: Aug 27, 2015Filed: Oct 30, 2017Granted: Aug 13, 2019
Est. expiryAug 27, 2035(~9.1 yrs left)· nominal 20-yr term from priority
Inventors:Akira Yajima
H10W 72/552H10W 72/884H10W 90/754H10W 72/877H10W 72/859H10W 90/753H10W 72/944H10W 72/953H10W 72/932H10W 72/922H10W 72/952H10W 72/29H10W 72/59H10W 72/9415H10W 72/923H10W 72/019H10W 72/01904H10W 70/656H10W 70/60H10W 70/05H10W 90/00H10W 72/012H10W 90/722H10W 72/252H10W 72/244H10W 72/242H10W 72/547H10W 72/07554H10W 72/247H10W 72/07254H10W 80/743H10P 95/90H10P 95/00H10P 74/207H10W 74/147H10W 72/075H10W 72/50H10W 72/20H10W 72/015H10W 20/40H10W 72/00H10P 74/273G11C 29/06G11C 29/48G11C 2029/5602H01L 25/0657H01L 2224/02331H01L 21/47635H01L 24/49H01L 22/32H01L 2224/03009H01L 24/43H01L 2224/73253H01L 2224/73207H01L 24/85H01L 2224/04042H01L 2924/04941H01L 24/16H01L 25/0655H01L 2224/16145H01L 2224/451H01L 2224/0392H01L 2224/05022H01L 2224/05583H01L 2224/05655H01L 24/14H01L 2224/13021H01L 24/05H01L 2224/05186H01L 2224/48138H01L 2224/05686H01L 2924/00014H01L 2924/014H01L 2224/13022H01L 24/11H01L 21/324H01L 2224/13024H01L 24/06H01L 2224/05124H01L 22/14H01L 2224/05147H01L 24/03H01L 2224/05567H01L 24/48H01L 2224/131H01L 2224/73265H01L 2224/05554H01L 2224/06102H01L 23/3192H01L 2224/05548H01L 2224/02311H01L 2224/48091H01L 24/73H01L 2224/02377H01L 2224/0401H01L 2224/48227H01L 24/13G01R 31/2886G01R 1/0675H10W 72/30H10W 72/013
53
PatentIndex Score
0
Cited by
16
References
12
Claims

Abstract

To enhance reliability of a test by suppressing defective bonding of a solder in the test of a semiconductor device, a method of manufacturing the semiconductor device includes: preparing a semiconductor wafer that includes a first pad electrode provided with a first cap film and a second pad electrode provided with a second cap film. Further, a polyimide layer that includes a first opening on the first pad electrode and a second opening on the second pad electrode is formed, and then, a rearrangement wiring that is connected to the second pad electrode via the second opening is formed. Next, an opening is formed in the polyimide layer such that an organic reaction layer remains on each of the first pad electrode and a bump land of the rearrangement wiring, then heat processing is performed on the semiconductor wafer, and then, a bump is formed on the rearrangement wiring.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method of manufacturing a semiconductor device comprising:
 (a) forming a pad over a semiconductor substrate; 
 (b) forming a first insulating film over the semiconductor substrate, the first insulating film having a first opening exposing a first region of the pad and a second opening exposing a second region of the pad different from the first region; 
 (c) forming a metal film connected to the pad in the second opening, while covering the first opening with a mask layer; 
 (d) forming a second insulating film over the first insulating film so as to expose a part of the metal film; and 
 (e) disposing a conductive material on the part of the metal film exposed by the second insulating film, wherein 
 the step (d) comprises:
 (d1) forming the second insulating film over the first insulating film, 
 (d2) after the (d1), performing a probe test by using a probe needle, and 
 (d3) after the (d2), removing an organic reaction layer derived from the second insulating film remained on the part of the metal film. 
 
 
     
     
       2. The method of manufacturing a semiconductor device according to  claim 1 , wherein, in the step (d3), the organic reaction layer is removed by ashing. 
     
     
       3. The method of manufacturing a semiconductor device according to  claim 1 , wherein, before the step (d3), a thickness of the organic reaction layer derived from the second insulating film remained on the part of the metal film is about 100 nm. 
     
     
       4. The method of manufacturing a semiconductor device according to  claim 1 , wherein the step (d) further comprises step (d4) performing heat processing, after performing the step (d2) and before performing the step (d3), and
 wherein a temperature of the heat processing is greater than a melting point of the conductive material. 
 
     
     
       5. The method of manufacturing a semiconductor device according to  claim 1 , wherein the pad has a rectangular planar shape. 
     
     
       6. The method of manufacturing a semiconductor device according to  claim 1 , wherein the second insulating film is comprised of polyimide. 
     
     
       7. The method of manufacturing a semiconductor device according to  claim 1 , wherein a size of the first opening is larger than a size of the second opening in plan view. 
     
     
       8. The method of manufacturing a semiconductor device according to  claim 1 , wherein the metal film is comprised of a Cu layer and a Ni layer formed on the Cu layer. 
     
     
       9. The method of manufacturing a semiconductor device according to  claim 1 , wherein the pad is an Al pad. 
     
     
       10. The method of manufacturing a semiconductor device according to  claim 1 , wherein the second insulating film has a fourth opening communicating with the first opening. 
     
     
       11. The method of manufacturing a semiconductor device according to  claim 1 , wherein the second insulating film has a third opening communicating with the second opening. 
     
     
       12. The method of manufacturing a semiconductor device according to  claim 1 , wherein the conductive material is a bump.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.