Semiconductor memory device

Abstract

A semiconductor memory device according to an embodiment comprises: when three directions intersecting each other are assumed to be first through third directions, and two directions intersecting each other in a plane extending in the first and second directions are assumed to be fourth and fifth directions, a memory cell array including: a conductive layer stacked in the third direction above a semiconductor substrate and having a first region; and a first columnar body penetrating the first region of the conductive layer in the third direction and including a semiconductor film, the first columnar body having a cross-section along the first and second directions in which, at a first position which is a certain position in the third direction, a length in the fourth direction is shorter than a length in the fifth direction.

What is claimed is: 
     
       1. A semiconductor memory device, comprising:
 when a first direction and a second direction intersect each other, and a third direction is orthogonal to the first and second directions, 
 a memory cell array including: a conductive layer stacked in the third direction above a semiconductor substrate and extending in the first direction; a first semiconductor body extending in the third direction and including a semiconductor film; and a memory portion provided between the first semiconductor body and the conductive layer, 
 the conductive layer having a side surface facing the second direction, and 
 the first semiconductor body having a cross-section along the first and second directions in which, at a first position which is a certain position in the third direction, a length in the first direction is shorter than a length in the second direction. 
 
     
     
       2. The semiconductor memory device according to  claim 1 , wherein
 the first semiconductor body has the cross-section in which, at the first position, the length in the second direction is 1.3 or more times the length in the first direction. 
 
     
     
       3. The semiconductor memory device according to  claim 1 , wherein
 the memory cell array has a first region in which the first semiconductor body is disposed, and a second region aligned in the first direction with the first region, 
 the memory cell array includes a columnar body extending in the third direction in the second region, and the columnar body has a cross-section along the first and second directions in which, at the first position, the length in the first direction is shorter than the length in the second direction. 
 
     
     
       4. The semiconductor memory device according to  claim 1 , wherein
 the memory cell array has a first region in which the first semiconductor body is disposed, and a second region aligned in the first direction with the first region, 
 the memory cell array includes a columnar body extending in the third direction in the second region, and 
 the columnar body has a cross-section along the first and second directions in which, at the first position, the length in the first direction is longer than the length in the second direction. 
 
     
     
       5. The semiconductor memory device according to  claim 1 , wherein
 the memory cell array has a first region in which the first semiconductor body is disposed, and a second region aligned in the first direction with the first region, 
 the memory cell array includes a columnar body extending in the third direction in the second region, and 
 the columnar body has a cross-section along the first and second directions which, at the first position, has a substantially circular shape. 
 
     
     
       6. The semiconductor memory device according to  claim 1 , wherein
 the first semiconductor body includes a tunnel insulating film and a charge accumulation film disposed between the semiconductor film and the conductive layer. 
 
     
     
       7. The semiconductor memory device according to  claim 1 , wherein
 the conductive layer adopts tungsten (W) as a material. 
 
     
     
       8. The semiconductor memory device according to  claim 1 , wherein
 the memory cell array includes a plurality of the conductive layers stacked in the third direction above the semiconductor substrate, via an inter-layer insulating layer. 
 
     
     
       9. A semiconductor memory device, comprising:
 when a first direction and a second direction intersect each other, and a third direction is orthogonal to the first and second directions, 
 a memory cell array including: a conductive layer stacked in the third direction above a semiconductor substrate and extending in the first direction; a plurality of first semiconductor bodies extending in the third direction and including a semiconductor film; and a plurality of memory portions provided between the first semiconductor bodies and the conductive layer, 
 the conductive layer having a side surface facing the second direction, 
 one of the plurality of first semiconductor bodies having a cross-section along the first and second directions in which, at a first position which is a certain position in the third direction, a length in the first direction is shorter than a length in the second direction, 
 the plurality of first semiconductor bodies including: a second semiconductor body; a third semiconductor body aligned in the first direction with the second semiconductor body; and a fourth semiconductor body disposed in between the second and third semiconductor bodies in the first direction and disposed at a different position to the second and third semiconductor bodies in the second direction, and 
 at a first position which is a certain position in the third direction, a spacing between the second and third semiconductor bodies being longer than a spacing between the second and third semiconductor bodies. 
 
     
     
       10. The semiconductor memory device according to  claim 9 , wherein
 at the first position, the spacing between the second and third semiconductor bodies is two or more times the spacing between the second and fourth semiconductor bodies. 
 
     
     
       11. The semiconductor memory device according to  claim 9 , wherein
 one of the plurality of first semiconductor bodies has the cross-section in which, at the first position, the length in the second direction is 1.3 or more times the length in the first direction. 
 
     
     
       12. The semiconductor memory device according to  claim 9 , wherein
 the memory cell array has a first region in which one of the plurality of first semiconductor bodies is disposed, and a second region aligned in the first direction with the first region, 
 the memory cell array includes a columnar body extending in the third direction in the second region, and the columnar body has a cross-section along the first and second directions which, at the first position, has a substantially circular shape. 
 
     
     
       13. The semiconductor memory device according to  claim 9 , wherein
 each of the plurality of first semiconductor bodies includes a tunnel insulating film and a charge accumulation film disposed between the semiconductor film and the conductive layer. 
 
     
     
       14. The semiconductor memory device according to  claim 9 , wherein
 the memory cell array includes a plurality of the conductive layers stacked in the third direction above the semiconductor substrate, via an inter-layer insulating layer. 
 
     
     
       15. A semiconductor memory device, comprising:
 when a first direction and a second direction intersect each other, and a third direction is orthogonal to the first and second directions, 
 a memory cell array including: a conductive layer stacked in the third direction above a semiconductor substrate and extending in the first direction; a first semiconductor body extending in the third direction and including a semiconductor film; and a memory portion provided between the first semiconductor body and the conductive layer, 
 the conductive layer having a side surface facing the second direction, and 
 the first semiconductor body having a cross-section along the first and second directions which, at a first position which is a certain position in the third direction, has an oval shape having a long axis along the second direction. 
 
     
     
       16. The semiconductor memory device according to  claim 15 , wherein
 the first semiconductor body has the cross-section in which, at the first position, a length of a long axis is 1.3 or more times a length of a short axis. 
 
     
     
       17. The semiconductor memory device according to  claim 15 , wherein
 the memory cell array has a first region in which the first semiconductor body is disposed, and a second region aligned in the first direction with the first region, 
 the memory cell array includes a columnar body extending in the third direction in the second region, and 
 the columnar body has a cross-section along the first and second directions which, at the first position, has the oval shape having a long axis along the second direction. 
 
     
     
       18. The semiconductor memory device according to  claim 15 , wherein
 the memory cell array has a first region in which the first semiconductor body is disposed, and a second region aligned in the first direction with the first region, 
 the memory cell array includes a columnar body extending in the third direction in the second region, and 
 the columnar body has a cross-section along the first and second directions which, at the first position, has the oval shape having a long axis along the first direction. 
 
     
     
       19. The semiconductor memory device according to  claim 15 , wherein
 the first semiconductor body includes a tunnel insulating film and a charge accumulation film disposed between the semiconductor film and the conductive layer. 
 
     
     
       20. The semiconductor memory device according to  claim 15 , wherein
 the memory cell array includes a plurality of the conductive layers stacked in the third direction above the semiconductor substrate, via an inter-layer insulating layer.