US10381827B2ActiveUtilityA1

Semiconductor integrated circuit device

33
Assignee: FUJI ELECTRIC CO LTDPriority: Jun 16, 2016Filed: May 31, 2017Granted: Aug 13, 2019
Est. expiryJun 16, 2036(~9.9 yrs left)· nominal 20-yr term from priority
H03K 19/00315H02H 11/003H02H 3/202H03K 3/356H02H 9/046H10W 20/43H10W 20/20H01L 23/528H01L 27/0629H01L 27/0285H01L 21/823418H01L 27/0266H01L 27/088H01L 27/0255H01L 27/0883H10D 84/83H10D 84/038H10D 84/013H10D 89/819H10D 89/811H10D 89/611H10D 84/811H10D 84/84H10D 89/10H10D 62/105
33
PatentIndex Score
0
Cited by
16
References
11
Claims

Abstract

A protection circuit includes a first PMOS and a first PDMOS receiving input of voltage of a voltage dividing point of voltage input from an external power supply terminal, and a second PMOS and a second PDMOS receiving input of drain output voltage of the first PDMOS. The first PMOS is connected on the external power supply terminal side of the first PDMOS, and the second PMOS is connected on the external power supply terminal side of the second PDMOS. During overvoltage application, the voltage of the voltage dividing point is clamped to the breakdown voltage of a Zener diode, the second PDMOS turns OFF, and supply to an integrated circuit protected from overvoltage is cut off. When the voltage source is connected in reverse, parasitic diodes of the first and second PMOSs are reverse-biased and the flow of current in a path through the parasitic diodes is inhibited.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A semiconductor integrated circuit device comprising:
 an external power supply terminal supplied a power supply voltage from outside the semiconductor integrated circuit device, in a steady-state; 
 a ground terminal supplied a ground voltage from outside the semiconductor integrated circuit device, in the steady-state; 
 an internal power supply terminal supplying, to an integrated circuit to be protected, the power supply voltage supplied from outside the semiconductor integrated circuit device, in the steady-state; 
 a voltage divider dividing voltage supplied from the external power supply terminal, the voltage divider connected between the external power supply terminal and the ground terminal; 
 a signal generator including an inverter circuit formed by a serially-connected member formed by connecting a first end of a first resistor element to a drain terminal of a first metal oxide semiconductor field effect transistor connected between the external power supply terminal and the ground terminal, the first metal oxide semiconductor field effect transistor outputting any one of the power supply voltage and the ground voltage according to a voltage of a voltage dividing point of the voltage divider, the first metal oxide semiconductor field effect transistor having, as an input terminal, a gate terminal connected to the voltage dividing point, and having a drain terminal as an output terminal; and 
 a switch switching output of the signal generator, the switch including a second metal oxide semiconductor field effect transistor connected between the external power supply terminal and the ground terminal, a drain terminal of the second metal oxide semiconductor field effect transistor being connected to the internal power supply terminal, and a gate terminal of the second metal oxide semiconductor field effect transistor being connected to a connection point of the drain terminal of the first metal oxide semiconductor field effect transistor and the first end of the first resistor element, wherein 
 the signal generator further includes a third metal oxide semiconductor field effect transistor, a drain terminal of the third metal oxide semiconductor field effect transistor being connected to the external power supply terminal, a source terminal of the third metal oxide semiconductor field effect transistor being connected to a source terminal of the first metal oxide semiconductor field effect transistor, and a gate terminal of the third metal oxide semiconductor field effect transistor being connected to the voltage dividing point, and 
 the switch further includes a fourth metal oxide semiconductor field effect transistor, a drain terminal of the fourth metal oxide semiconductor field effect transistor being connected to the external power supply terminal, a source terminal of the fourth metal oxide semiconductor field effect transistor being connected to a source terminal of the second metal oxide semiconductor field effect transistor, and a gate terminal of the fourth metal oxide semiconductor field effect transistor being connected to the connection point. 
 
     
     
       2. The semiconductor integrated circuit device according to  claim 1 , wherein
 the third metal oxide semiconductor field effect transistor is an enhancement-type p-channel metal oxide semiconductor field effect transistor. 
 
     
     
       3. The semiconductor integrated circuit device according to  claim 1 , wherein
 the fourth metal oxide semiconductor field effect transistor is an enhancement-type p-channel metal oxide semiconductor field effect transistor. 
 
     
     
       4. The semiconductor integrated circuit device according to  claim 1 , wherein
 the third metal oxide semiconductor field effect transistor is a depression-type p-channel metal oxide semiconductor field effect transistor. 
 
     
     
       5. The semiconductor integrated circuit device according to  claim 1 , wherein
 the fourth metal oxide semiconductor field effect transistor is a depression-type p-channel metal oxide semiconductor field effect transistor. 
 
     
     
       6. The semiconductor integrated circuit device according to  claim 4 , wherein
 a gate threshold voltage of the fourth metal oxide semiconductor field effect transistor is set so that a voltage applied to the gate terminal of the fourth metal oxide semiconductor field effect transistor becomes higher than a voltage applied to the source terminal of the fourth metal oxide semiconductor field effect transistor, when the ground voltage is supplied to the external power supply terminal and the power supply voltage is supplied to the ground terminal. 
 
     
     
       7. The semiconductor integrated circuit device according to  claim 1 , wherein
 the first metal oxide semiconductor field effect transistor and the second metal oxide semiconductor field effect transistor are each an enhancement-type p-channel metal oxide semiconductor field effect transistor. 
 
     
     
       8. The semiconductor integrated circuit device according to  claim 1 , wherein
 the voltage divider includes another serially-connected member in which a Zener diode is connected in series to a second resistor element, and 
 a breakdown voltage of the Zener diode is a maximum rated voltage of the integrated circuit or less. 
 
     
     
       9. The semiconductor integrated circuit device according to  claim 1 , wherein
 the integrated circuit includes a plurality of metal oxide semiconductor field effect transistors. 
 
     
     
       10. The semiconductor integrated circuit device according to  claim 1 , wherein
 the voltage divider, the signal generator, and the switch are formed on a single semiconductor substrate with the integrated circuit. 
 
     
     
       11. The semiconductor integrated circuit device according to  claim 5 , wherein
 a gate threshold voltage of the fourth metal oxide semiconductor field effect transistor is set so that a voltage applied to the gate terminal of the fourth metal oxide semiconductor field effect transistor becomes higher than a voltage applied to the source terminal of the fourth metal oxide semiconductor field effect transistor, when the ground voltage is supplied to the external power supply terminal and the power supply voltage is supplied to the ground terminal.

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