Readout voltage uncertainty compensation in time-of-flight imaging pixels

Abstract

Pixel arrangements in time-of-flight sensors are presented that include sensing elements that establish charges related to incident light, charge storage elements that accumulate integrated charges transferred from the sensing elements, and diffusion nodes configured to establish measurement voltages representative of the integrated charges that are dumped from the charge storage elements. The pixel arrangement includes analog domain output circuitry comprising a measurement capacitance element that stores the measurement voltage, and a reset capacitance element that stores a reset voltage established at the diffusion node during a reset phase performed prior to a measurement phase. The analog domain output circuitry subtracts the stored reset voltage from the stored measurement voltage for processing into a pixel output voltage that at least partially reduces readout voltage uncertainty of the pixel arrangement.

What is claimed is: 
     
       1. A pixel arrangement in a time-of-flight sensor, comprising:
 a polysilicon sensing element of a differential pixel structure configured to establish charges related to incident light during a measurement phase; 
 a charge storage element configured to accumulate integrated charges of the measurement phase transferred from the polysilicon sensing element; 
 a diffusion node configured to establish a measurement voltage representative of ones of the integrated charges established during the measurement phase that are dumped from the charge storage element; and 
 analog domain output circuitry comprising a measurement capacitance element that stores the measurement voltage, and a reset capacitance element that stores a reset voltage established at the diffusion node during a reset phase performed prior to the measurement phase; 
 the analog domain output circuitry configured to subtract the reset voltage stored in the reset capacitance element from the measurement voltage stored in the measurement capacitance element to establish a compensated result that at least partially reduces readout voltage uncertainty of the pixel arrangement, and provide the compensated result for processing into a pixel output voltage differentially derived with at least a further compensated result associated with a further polysilicon sensing element of the differential pixel structure during an associated measurement phase. 
 
     
     
       2. The pixel arrangement of  claim 1 , further comprising:
 a bias gate element that establishes a bias potential between the polysilicon sensing element and the charge storage element to provide a pathway for transfer of at least a portion of the charges established at the polysilicon sensing element to the charge storage element and reduce a quantity of the charges transferred to the charge storage element from returning to the polysilicon sensing element; and 
 a transfer gate element, based on activation, establishes a transfer potential between at least the charge storage element and the diffusion node to dump the ones of the integrated charges stored at the charge storage element to the diffusion node. 
 
     
     
       3. The pixel arrangement of  claim 2 , wherein the charge storage element comprises a polysilicon capacitor element formed with an underlying p-type dopant well of a higher p-type doping level than a semiconductor substrate associated with the pixel arrangement; and
 wherein a bias on the charge storage element establishes a higher potential level than the bias potential of the bias gate element to provide the pathway for at least the portion of the charges established at the polysilicon sensing element to be transferred to the charge storage element from the polysilicon sensing element. 
 
     
     
       4. The pixel arrangement of  claim 1 , wherein the readout voltage uncertainty of the pixel arrangement comprises a kTC noise associated with a readout capacitance of the pixel arrangement. 
     
     
       5. The pixel arrangement of  claim 1 , further comprising:
 a reset gate, based on activation during the reset phase, drains to a voltage source at least a portion of intervening charges established at the polysilicon sensing element to provide an anti-blooming function to the pixel arrangement. 
 
     
     
       6. The pixel arrangement of  claim 1 , wherein the analog domain output circuitry further comprises:
 differential amplifier circuitry configured to derive the pixel output voltage as a differential voltage among the compensated result and the further compensated result. 
 
     
     
       7. The pixel arrangement of  claim 1 , wherein the analog domain output circuitry is further configured to provide the pixel output voltage to an analog-to-digital converter for conversion of the pixel output voltage as an analog pixel representation into a digital pixel representation. 
     
     
       8. The pixel arrangement of  claim 7 , wherein the digital pixel representation is processed along with at least further digital pixel representations of further pixel arrangements of the time-of-flight sensor to determine a time-of-flight measurement for a scene presented to the time-of-flight sensor. 
     
     
       9. A time-of-flight (ToF) imaging sensor, comprising:
 a semiconductor substrate; 
 an array of differential pixel structures for sensing at least incident light that are each configured to produce associated reset voltages resultant from associated reset phases and associated measurement voltages resultant from associated measurement phases performed after the associated reset phases; 
 capacitance elements that store ones of the measurement voltages and ones of the reset voltages; and 
 readout circuitry configured to establish compensated voltages that at least partially reduces readout voltage uncertainty for each of the differential pixel structures based at least on subtracting associated stored ones of the reset voltages from associated stored ones of the measurement voltages, and determine differential voltages among the compensated voltages for each of the differential pixel structures as pixel output voltages; 
 wherein each of the differential pixel structures comprise: 
 at least two polysilicon sensing elements configured to establish charges related to incident light during corresponding ones of the measurement phases; 
 charge storage elements each configured to accumulate integrated charges based at least on ones of the charges transferred from an associated polysilicon sensing element; 
 diffusion nodes each configured to produce the associated measurement voltages based at least on ones of the integrated charges dumped from an associated charge storage element, and produce the associated reset voltages established at the diffusion nodes. 
 
     
     
       10. The ToF imaging sensor of  claim 9 , wherein each of the differential pixel structures further comprise:
 bias gate elements each configured to establish a bias potential between the associated polysilicon sensing element and the associated charge storage element to provide a pathway for transfer of at least a portion of the charges established at the associated polysilicon sensing element to the associated charge storage element and reduce a quantity of the charges transferred to the associated charge storage element from returning to the associated polysilicon sensing element; and 
 transfer gate elements, based on activation, are each configured to establish a transfer potential between the associated charge storage element and the associated diffusion node to dump the ones of the integrated charges stored at the associated charge storage element to the associated diffusion node. 
 
     
     
       11. The ToF imaging sensor of  claim 10 , wherein the charge storage elements each comprise a polysilicon capacitor element formed with an underlying p-type dopant well of a higher p-type doping level than the semiconductor substrate; and
 wherein biases on the charge storage elements establish a higher potential level than the bias potential of an associated bias gate element to provide the pathway for at least the portion of the charges established at the associated polysilicon sensing element to be transferred to the associated charge storage element from the associated polysilicon sensing element. 
 
     
     
       12. The ToF imaging sensor of  claim 9 , wherein the readout voltage uncertainty for each of the differential pixel structures comprises a kTC noise associated with a readout capacitance of the associated diffusion nodes. 
     
     
       13. The ToF imaging sensor of  claim 9 , wherein each of the differential pixel structures further comprise:
 at least one gate, based on activation during the associated reset phases, drains to a voltage source at least a portion of intervening charges established at an associated polysilicon sensing element to provide an anti-blooming feature. 
 
     
     
       14. The ToF imaging sensor of  claim 9 , wherein the readout circuitry provides the pixel output voltages to analog-to-digital converter circuitry for conversion of the pixel output voltages as analog pixel representations into digital pixel representations, wherein the digital pixel representations are processed to determine a time-of-flight measurement for a scene presented to the ToF imaging sensor. 
     
     
       15. A method of operating a time-of-flight (ToF) imaging pixel arrangement formed on a semiconductor substrate, the method comprising:
 at least two polysilicon sensing elements of a differential pixel structure each establishing charges related to incident light during corresponding differential measurement phases; 
 charge storage elements each accumulating integrated charges transferred from an associated polysilicon sensing element; 
 diffusion nodes each establishing measurement voltages based at least on ones of the integrated charges dumped from an associated charge storage element; 
 first capacitance elements each storing reset voltages established at associated ones of the diffusion nodes prior to transfer of the ones of the integrated charges to the associated ones of the diffusion nodes; 
 second capacitance elements each storing the measurement voltages established at the associated ones of the diffusion nodes after transfer of the ones of the integrated charges to the associated ones of the diffusion nodes; 
 analog output circuitry subtracting corresponding ones of the reset voltages stored in the first capacitance elements from ones of the measurement voltages stored in the second capacitance elements to establish compensated results that at least partially cancel readout voltage uncertainty of the pixel arrangement corresponding to each of the differential measurement phases; and 
 the analog output circuitry determining differential voltages among the compensated results to establish pixel output voltages. 
 
     
     
       16. The method of  claim 15 , further comprising:
 bias gate elements each establishing a bias potential between an associated polysilicon sensing element and an associated charge storage element to provide a pathway for transfer of at least a portion of the charges established at the associated polysilicon sensing element to the associated charge storage element and reduce a quantity of the charges transferred to the associated charge storage element from returning to the associated polysilicon sensing element; and 
 transfer gate elements each establishing a transfer potential between the associated charge storage element and the associated diffusion node to dump the ones of the integrated charges stored at the associated charge storage element to the associated diffusion node. 
 
     
     
       17. The method of  claim 16 , wherein the charge storage elements each comprise a polysilicon capacitor element formed with an underlying p-type dopant well of a higher p-type doping level than the semiconductor substrate; and
 wherein biases on the charge storage elements establish a higher potential level than the bias potential of an associated bias gate element to provide the pathway for at least the portion of the charges established at the associated polysilicon sensing element to be transferred to the associated charge storage element from the associated polysilicon sensing element. 
 
     
     
       18. The method of  claim 15 , wherein the readout voltage uncertainty of the pixel arrangement comprises a kTC noise associated with a readout capacitance of the associated ones of the diffusion nodes. 
     
     
       19. The method of  claim 15 , further comprising:
 at least one reset gate draining to a voltage source at least a portion of intervening charges established at an associated polysilicon sensing element based on activation during an associated reset phase to provide an anti-blooming feature to the pixel arrangement. 
 
     
     
       20. The method of  claim 15 , further comprising:
 the analog output circuitry providing the pixel output voltages to analog-to-digital converter circuitry for conversion of the pixel output voltages as analog pixel representations into digital pixel representations, wherein the digital pixel representations are processed to determine a time-of-flight measurement for a scene presented to the ToF imaging sensor.