Drive voltage booster

Abstract

This disclosure describes a gate driver with voltage boosting capabilities. In some embodiments, the gate driver may comprise a charge pump that includes capacitor(s) and switch(es). Responsive a logic low input signal, the gate driver may bypass the capacitor(s) to allow the input digital signal to drive the gating signal directly. Conversely, responsive to a logic high input signal, the gate driver may couple the capacitor(s) in series with the input digital signal to generate a boosted gating signal. In some embodiments, the gate driver may comprise an inductor-capacitor resonant circuit to create a doubled output gating signal with respect to the input digital signal. In some embodiments, the resonant gate driver may include an additional voltage boosting capability that can be selectively enabled to compensate for a voltage drop during the signal transfer from the input to the output.

The invention claimed is: 
     
       1. A gate driver with voltage boosting capabilities for generating a gating signal at an output of the gate driver from an input signal received at an input of the gate driver, the gate driver comprising:
 a charge pump, the charge pump comprising a capacitor and a plurality of switches; 
 wherein responsive to a low value of an input signal, the capacitor is bypassed by the plurality of switches as to allow the input signal to drive the output directly, and 
 wherein responsive to a high value of the input signal, the capacitor is coupled in series with the input signal by the plurality of switches to drive the output with a boosted value with respect to the input signal. 
 
     
     
       2. The gate driver of  claim 1 , wherein
 the plurality of switches comprises at least two series-connected switches; 
 the capacitor is coupled across at least one of the at least two series-connected switches; 
 responsive to the low value of the input signal, the capacitor is bypassed by a first switch or a body diode of the first switch of the at least two series-connected switches; and 
 responsive to the high value of the input signal, the capacitor is coupled in series with the input signal by a second switch of the at least two series-connected switches. 
 
     
     
       3. The gate driver of  claim 2 , further comprising a first diode, wherein
 the first diode is coupled in parallel with the first switch of the at least two series-connected switches; and 
 responsive to the low value of the input signal, the capacitor is bypassed by the first diode. 
 
     
     
       4. The gate driver of  claim 1 , further comprising a bias voltage that is configured to charge the charge pump. 
     
     
       5. The gate driver of  claim 1 , further comprising a diode coupled in series with a bias voltage and configured to block a discharging of the charge pump responsive to the high value of the input signal. 
     
     
       6. The gate driver of  claim 4 , wherein the bias voltage is equivalent or close to a steady-state high voltage of the input signal. 
     
     
       7. The gate driver of  claim 4 , wherein the bias voltage is different from a steady-state high voltage of the input signal. 
     
     
       8. A method for generating a gating signal, comprising:
 receiving an input signal by a gate driver, the gate driver comprising a charge pump that includes a capacitor and a plurality of switches; 
 responsive to a low value of the input signal, bypassing the capacitor of the charge pump by operating the plurality of switches so as to directly couple the input signal to an output of the gate driver; and 
 responsive to a high value of the input signal, coupling the capacitor of the charge pump in series with the input signal and the output of the gate driver by operating the plurality of switches to generate the gating signal with a boosted value with respect to the input signal. 
 
     
     
       9. The method of  claim 8 , wherein
 the plurality of switches comprises at least two series-connected switches; 
 the capacitor is coupled across at least one of the at least two series-connected switches; 
 bypassing the capacitor, responsive to the low value of the input signal, comprises closing a first switch or conducting current through a body diode of the first switch of the at least two series-connected switches; and 
 coupling the capacitor in series with the input signal, responsive to the high value of the input signal, comprises closing a second switch of the at least two series-connected switches. 
 
     
     
       10. The method of  claim 9 , wherein
 the gate driver further comprises a first diode that is coupled in parallel with the first switch of the at least two series-connected switches; and 
 bypassing the capacitor, responsive to the low value of the input signal, comprises conducting current through the first diode. 
 
     
     
       11. The method of  claim 8 , wherein the gate driver further comprises a bias voltage that is configured to charge the charge pump. 
     
     
       12. The method of  claim 8 , wherein the gate driver further comprises a diode coupled in series with the bias voltage and configured to block a discharging of the charge pump responsive to the high value of the input signal. 
     
     
       13. The method of  claim 11 , wherein the bias voltage is equivalent or close to a steady-state high voltage of the input signal. 
     
     
       14. The method of  claim 11 , wherein the bias voltage is different from a steady-state high voltage of the input signal. 
     
     
       15. A gate driver with voltage boosting capabilities for generating a gating signal from an input signal, comprising:
 a charge pump, the charge pump comprising at least two series-connected switches, a capacitor coupled across at least one of the at least two series-connected switches, and a first diode coupled in parallel with a first switch of the at least two series-connected switches; 
 wherein responsive to a low value of an input signal, the capacitor is bypassed by the plurality of switches and the first diode so as to allow the input signal to be the gating signal, and 
 wherein responsive to a high value of the input signal, the capacitor is coupled in series with the input signal by the plurality of switches to generate the gating signal with a boosted value with respect to the input signal. 
 
     
     
       16. The gate driver of  claim 15 , further comprising a bias voltage that is configured to charge the charge pump. 
     
     
       17. The gate driver of  claim 16 , further comprising a diode coupled in series with the bias voltage and configured to block a discharging of the charge pump responsive to the high value of the input signal. 
     
     
       18. The gate driver of  claim 16 , wherein the bias voltage is equivalent or close to a steady-state high voltage of the input signal. 
     
     
       19. The gate driver of  claim 16 , wherein the bias voltage is different from a steady-state high voltage of the input signal.