Semiconductor memory device and method of manufacturing the same

Abstract

Provided is a semiconductor device, which prevents unnecessary voltage drop in a MOS transistor that is connected in series in a location between a booster circuit and a memory main body portion, to thereby operate on a low voltage and improve the ON/OFF ratio so that chip size shrinking and memory performance improvement are accomplished simultaneously. In a semiconductor memory device including a memory transistor portion and a select transistor portion, at least the select transistor portion is formed of a fin-shaped single-crystal semiconductor thin film.

What is claimed is: 
     
       1. A semiconductor memory device, comprising:
 a select transistor portion comprising:
 a first fin-shaped single-crystal semiconductor thin film formed of a semiconductor substrate of a first conductivity type; 
 a drain region of a second conductivity type formed on a surface of the first fin-shaped single-crystal semiconductor thin film; 
 a tunnel drain region of the second conductivity type formed on the surface of the first fin-shaped single-crystal semiconductor thin film apart from the drain region; and 
 a select gate formed between the drain region and the tunnel drain region, the select gate overlying an upper surface and side surfaces of the first fin-shaped single-crystal semiconductor thin film with a select gate oxide film interposed between the select gate and the first fin-shaped single-crystal semiconductor thin film, 
 wherein a region lower in concentration than that of the drain region is formed on the upper surface and side surfaces of the first fin-shaped single-crystal semiconductor thin film under the select gate; and 
 
 a memory transistor portion comprising:
 a second fin-shaped single-crystal semiconductor thin film formed of the semiconductor substrate; 
 a source region of the second conductivity type formed on a surface of the second fin-shaped single-crystal semiconductor thin film; 
 a floating gate formed above the second fin-shaped single-crystal semiconductor thin film with a gate oxide film interposed between the second fin-shaped single-crystal semiconductor thin film and the floating gate, the gate oxide film being spaced from and not contacting the select gate oxide film and being disposed on a surface of the tunnel drain region and extending from the surface of the tunnel drain region to an edge of the source region, the gate oxide film being formed on an upper surface and side surfaces of the second fin-shaped single-crystal semiconductor thin film, and the part of the gate oxide film disposed on the surface of the tunnel drain region comprising a tunnel insulating film; and 
 
 a control gate formed above the floating gate with an insulating film interposed between the floating gate and the control gate. 
 
     
     
       2. A semiconductor memory device according to  claim 1 , wherein the select gate comprises a lower select gate and an upper select gate that is electrically connected to the lower select gate.