Resistance change type memory

Abstract

A resistance change type memory device includes a first memory cell at a crossing of a first bit line and a first word line, a second memory cell at a crossing of a second bit line and a second word line, a first selection gate line connected to the first bit line, a second selection gate line connected to the second bit line, a dummy gate line adjacent to the first selection gate line, and a control circuit configured to apply a first voltage to the first selection gate line and a second voltage smaller than the first voltage to the dummy gate line when the first selection gate line is selected, and the second voltage or a third voltage smaller than the second voltage to the first selection gate line and the third voltage to the dummy gate line when the second selection gate line is selected.

What is claimed is: 
     
       1. A resistance change type memory device, comprising:
 a first bit line extending along a first direction perpendicular to a surface of a substrate; 
 a second bit line extending along the first direction in parallel with the first bit line; 
 a dummy bit line extending along the first direction in parallel with the first bit line and the second bit line, the first bit line, the second bit line, and the dummy bit line being spaced from each other in a second direction parallel to the surface of the substrate; 
 a first word line extending along a third direction parallel to the surface of the substrate; 
 a second word line extending along the third direction in parallel with the first word line; 
 a first memory cell at a crossing of the first bit line and the first word line; 
 a second memory cell at a crossing of the second bit line and the second word line; 
 a first selection transistor between the first bit line and the substrate in the first direction, the first selection transistor having a first channel portion and a first gate portion connected to a first selection gate line; 
 a second selection transistor between the second bit line and the substrate in the first direction, the second selection transistor having a second channel portion and a second gate portion connected to a second selection gate line; 
 a dummy selection transistor between the dummy bit line and the substrate in the first direction, the dummy selection transistor having a dummy channel portion and a dummy gate portion connected to a dummy selection gate line, the dummy selection gate line being adjacent to the first selection gate line in the second direction and not adjacent to the second selection gate line in the second direction; and 
 a control circuit configured to apply:
 when the first selection gate line is selected, a first voltage to the first selection gate line, and a second voltage to the dummy selection gate line, the second voltage being smaller than the first voltage, and 
 when the second selection gate line is selected, the first voltage to the second selection gate line, the second voltage or a third voltage to the first selection gate line, and the third voltage to the dummy selection gate line, the third voltage being equal to or smaller than the second voltage. 
 
 
     
     
       2. The memory device according to  claim 1 , wherein
 when the second selection gate line is selected and adjacent to the first selection gate line, the first control circuit applies the second voltage to the first selection gate line, and 
 when the second selection gate line is selected and not adjacent to the first selection gate line, the first control circuit applies the third voltage to the first selection gate line. 
 
     
     
       3. The memory device according to  claim 1 , wherein the control circuit comprises:
 a first decode circuit configured to apply to the first selection gate line:
 the first voltage based on a first signal when the first selection gate line is selected, and 
 the second voltage or the third voltage based on a second signal when the second selection gate line is selected. 
 
 
     
     
       4. The memory device according to  claim 3 , wherein the control circuit further comprises:
 a second decode circuit configured to apply to the dummy selection gate line:
 the second voltage to the dummy selection gate line based on the first signal when the first selection gate line is selected, and 
 the third voltage to the dummy selection gate line based on the second signal when the second selection gate line is selected. 
 
 
     
     
       5. The memory device according to  claim 3 , wherein the control circuit comprises:
 a second decode circuit including a first transistor of a first conductive type configured to output the second voltage and a second transistor of a second conductive type configured to output the third voltage, wherein 
 when the first signal is at a first level and the first transistor is in an ON state,
 the first selection gate line is selected, 
 the first decode circuit applies the first voltage to the first selection gate line, and 
 the second decode circuit applies the second voltage to the dummy selection gate line by the first transistor, and 
 
 when the first signal is at a second level and the second transistor is in an ON state,
 the second selection gate line is selected, 
 the first decode circuit applies the second voltage or the third voltage to the first selection gate line, and 
 the second circuit applies the third voltage to the dummy selection gate line by the second transistor. 
 
 
     
     
       6. The memory device according to  claim 1 , further comprising:
 a dummy word line extending along the third direction; and 
 a dummy memory cell at a crossing of the dummy bit line and the dummy word line, wherein 
 the dummy selection transistor is between the dummy bit line and the substrate in the first direction. 
 
     
     
       7. The memory device according to  claim 1 , wherein the dummy selection transistor has an upper portion in contact with an insulating layer on the substrate. 
     
     
       8. A resistance change type memory device, comprising:
 a first bit line extending along a first direction perpendicular to a surface of a substrate; 
 a second bit line extending along the first direction in parallel with the first bit line; 
 a dummy bit line extending along the first direction in parallel with the first bit line and the second bit line, the first bit line, the second bit line, and the dummy bit line being spaced from each other in a second direction parallel to the surface of the substrate; 
 a first conductive layer extending along a third direction parallel to the surface of the substrate; 
 a second conductive layer extending along the third direction in parallel with the first conductive layer; 
 a first memory cell at a crossing of the first bit line and the first conductive layer; 
 a second memory cell at a crossing of the second bit line and the second conductive layer; 
 a first selection transistor between the first memory cell and the substrate in the first direction, the first selection transistor having a first channel portion and a first gate portion connected to a first selection gate line; 
 a second selection transistor between the second memory cell and the substrate in the first direction, the second selection transistor having a second channel portion and a second gate portion connected to a second selection gate line; 
 a dummy selection transistor between the dummy bit line and the substrate in the first direction, the dummy selection transistor having a dummy channel portion and a dummy gate portion connected to a dummy selection gate line, the dummy selection gate line being adjacent to the first selection gate line in the second direction and not adjacent to the second selection gate line in the second direction; and 
 a control circuit configured to apply:
 when the first selection gate line is selected, a first voltage to the first selection gate line, and a second voltage to the dummy selection gate line, the second voltage being smaller than the first voltage, and 
 when the second selection gate line is selected, the first voltage to the second selection gate line, the second voltage or a third voltage to the first selection gate line, and the third voltage to the dummy selection gate line, the third voltage being equal to or smaller than the second voltage. 
 
 
     
     
       9. The memory device according to  claim 8 , further comprising:
 a first memory hole and a second memory hole extending through the first and second conductive layers in parallel along the first direction, wherein 
 the first and second bit lines pass through the first and second memory holes, respectively. 
 
     
     
       10. The memory device according to  claim 8 , wherein
 when the second selection gate line is selected and adjacent to the first selection gate line, the first control circuit applies the second voltage to the first selection gate line, and 
 when the second selection gate line is selected and not adjacent to the first selection gate line, the first control circuit applies the third voltage to the first selection gate line. 
 
     
     
       11. The memory device according to  claim 8 , wherein the control circuit comprises:
 a first decode circuit configured to apply to the first selection gate line:
 the first voltage based on a first signal when the first selection gate line is selected, and 
 the second voltage or the third voltage based on a second signal when the second selection gate line is selected. 
 
 
     
     
       12. The memory device according to  claim 11 , wherein the control circuit further comprises:
 a second decode circuit configured to apply to the dummy selection gate line:
 the second voltage to the dummy selection gate line based on the first signal when the first selection gate line is selected, and 
 the third voltage to the dummy selection gate line based on the second signal when the second selection gate line is selected. 
 
 
     
     
       13. The memory device according to  claim 11 , wherein the control circuit comprises:
 a second decode circuit including a first transistor of a first conductive type configured to output the second voltage and a second transistor of a second conductive type configured to output the third voltage, wherein 
 when the first signal is at a first level and the first transistor is in an ON state,
 the first selection gate line is selected, 
 the first decode circuit applies the first voltage to the first selection gate line, and 
 the second decode circuit applies the second voltage to the dummy selection gate line by the first transistor, and 
 
 when the first signal is at a second level and the second transistor is in an ON state,
 the second selection gate line is selected, 
 the first decode circuit applies the second voltage or the third voltage to the first selection gate line, and 
 the second circuit applies the third voltage to the dummy selection gate line by the second transistor. 
 
 
     
     
       14. The memory device according to  claim 8 , further comprising:
 a dummy word line extending along the third direction; and 
 a dummy memory cell at a crossing of the dummy bit line and the dummy word line, wherein 
 the dummy selection transistor is between the dummy bit line and the substrate in the first direction. 
 
     
     
       15. The memory device according to  claim 8 , wherein the dummy selection transistor has an upper portion in contact with an insulating layer on the substrate. 
     
     
       16. A method for controlling a resistance change type memory device, comprising:
 applying a first voltage to the first selection gate line and a second voltage to a dummy selection gate line connected to a dummy selection transistor when the first selection gate line, which is connected to a first selection transistor and adjacent to the dummy selection gate line, is selected; and 
 applying the first voltage to a second selection gate line, the second voltage or a third voltage to the first selection gate line, and the third voltage to the dummy selection gate line when a second selection gate line connected to a second selection transistor and not adjacent to the dummy selection gate line is selected, wherein 
 the second voltage is smaller than the first voltage, and 
 the third voltage is equal to or smaller than the second voltage. 
 
     
     
       17. The method according to  claim 16 , further comprising:
 applying the second voltage to the first selection gate line when the second selection gate line is selected and adjacent to the first selection gate line; and 
 applying the third voltage to the first selection gate line when the second selection gate line is selected and not adjacent to the first selection gate line. 
 
     
     
       18. The method according to  claim 16 , further comprising:
 receiving a first signal and a second signal; 
 applying the first voltage based on the first signal to the first selection gate line when the first selection gate line is selected; and 
 applying the second voltage or the third voltage based on the second signal to the first selection gate line when the second selection gate line is selected. 
 
     
     
       19. The method according to  claim 18 , further comprising:
 applying the second voltage to the dummy selection gate line based on the first signal to the dummy selection gate line when the first selection gate line is selected; and 
 applying the third voltage to the dummy selection gate line based on the second signal to the dummy selection gate line when the second selection gate line is selected. 
 
     
     
       20. The method according to  claim 18 , further comprising:
 applying the first voltage to the first selection gate line when the first signal is at a first level and the first selection gate line is selected; 
 applying the second voltage to the dummy selection gate line when the first signal is at the first level and the first selection gate line is selected; 
 applying the second voltage or the third voltage to the first selection gate line when the first signal is at a second level and the second selection gate line is selected; and 
 applying the third voltage to the dummy selection gate line when the first signal is at the second level and the second selection gate line is selected.