Semiconductor integrated circuit

Abstract

In a monitor circuit, a data signal is propagated from an FF to another FF via a data delay circuit. The data delay circuit selects any one from among data paths that delay the data signal in accordance with a selection signal. A clock signal that is input to the FF is input to the other FF via a clock delay circuit. The clock delay circuit selects any one from among clock paths that delay the clock signal in accordance with another selection signal.

What is claimed is: 
     
       1. A semiconductor integrated circuit, comprising:
 a monitor circuit configured to determine presence or absence of a data propagation error, 
 the monitor circuit including: 
 a first flip-flop having a clock terminal receiving a first clock signal; 
 a data delay circuit configured to delay a first data signal that is an output of the first flip-flop; 
 a clock delay circuit configured to delay the first clock signal; and 
 a second flip-flop having (i) a data input terminal receiving an output signal of the data delay circuit, and (ii) a clock terminal receiving an output signal of the clock delay circuit, 
 the data delay circuit including: 
 a plurality of data paths each configured to delay the first data signal; and 
 a data selection circuit configured to select a data path among the plurality of data paths in accordance with a first selection signal, and output the first data signal that has transmitted through the selected data path as an output signal of the data delay circuit, and 
 the clock delay circuit including: 
 a plurality of clock paths each configured to delay the first clock signal; and 
 a clock selection circuit configured to select a clock path among the plurality of clock paths in accordance with a second selection signal, and output the first clock signal that has transmitted through the selected clock path as an output signal of the clock delay circuit. 
 
     
     
       2. The semiconductor integrated circuit of  claim 1 , wherein
 the monitor circuit includes: 
 a third flip-flop having a data input terminal receiving the first data signal, and a clock terminal receiving an output signal of the clock delay circuit; and 
 a determination circuit configured to determine whether an output signal of the second flip-flop and an output signal of the third flip-flop coincide with each other. 
 
     
     
       3. The semiconductor integrated circuit of  claim 1 , wherein
 the data delay circuit includes as elements constituting the plurality of data paths: 
 a gate delay unit having a gate constituting a circuit function as a delay element; and 
 a wiring delay unit not having a gate but having a wiring as a delay element. 
 
     
     
       4. The semiconductor integrated circuit of  claim 3 , further comprising
 a first region provided with the wiring delay unit and a second region provided with the gate delay unit, the first region and the second region being arranged so as not to have an overlap in planar view. 
 
     
     
       5. The semiconductor integrated circuit of  claim 3 , wherein
 the wiring delay unit includes a wiring having a shield wiring provided around the wiring. 
 
     
     
       6. The semiconductor integrated circuit of  claim 3 , wherein
 the data delay circuit comprises as the wiring delay unit: 
 a first delay unit including a plurality of paths each having a wiring formed in a first wiring layer as a delay element; and 
 a second delay unit including a plurality of paths each having a wiring formed in a second wiring layer different from the first wiring layer as a delay element, and 
 the data selection circuit comprises: 
 a first selection unit configured to select any one from among the plurality of paths belonging to the first delay unit; and 
 a second selection unit configured to select any one from among the plurality of paths belonging to the second delay unit. 
 
     
     
       7. The semiconductor integrated circuit of  claim 1 , wherein
 the monitor circuit outputs an output signal indicating a determination result, and 
 the semiconductor integrated circuit comprises an output holding circuit that holds an output signal of the monitor circuit for multiple times of determinations, and when the held output signals each indicate the absence of a data propagation error, determines that data propagation has been properly performed in the monitor circuit. 
 
     
     
       8. A semiconductor integrated circuit, comprising:
 a monitor circuit having first and second flip-flops, the monitor circuit being configured to determine presence or absence of a data propagation error in a critical path that is implemented in a simulated manner between the first and second flip-flops and output an output signal indicating a determination result; and 
 an output holding circuit configured to hold an output signal of the monitor circuit for multiple times of determinations, and when the held output signals each indicate the absence of a data propagation error, determine that data propagation has been properly performed in the monitor circuit.