Integrated circuitry construction, a DRAM construction, and a method used in forming an integrated circuitry construction

Abstract

An integrated circuitry construction comprises a substrate comprising conductive nodes of integrated circuitry. A conductive line structure is above the conductive nodes. Elevationally-extending conductive vias are spaced longitudinally along the conductive line structure. The conductive vias individually directly electrically couple the conductive line structure to individual of the conductive nodes. The conductive line structure comprises conductive material directly electrically coupled to the conductive vias and extending between immediately-longitudinally-adjacent of the conductive vias. An upper insulative material is directly below the conductive material between the immediately-longitudinally-adjacent conductive vias. Doped or undoped semiconductor material directly is below the upper insulative material between the immediately-longitudinally-adjacent conductive vias. A lower insulative material is directly below the semiconductor material between the immediately-longitudinally-adjacent conductive vias. Other aspects, including method, are disclosed.

The invention claimed is: 
     
       1. An integrated circuitry construction comprising:
 a substrate comprising conductive nodes of integrated circuitry; 
 a conductive line structure above the conductive nodes; and 
 elevationally-extending conductive vias spaced longitudinally along the conductive line structure, the conductive vias individually directly electrically coupling the conductive line structure to individual of the conductive nodes, the conductive line structure comprising:
 conductive material directly electrically coupled to the conductive vias and extending between immediately-longitudinally-adjacent of the conductive vias; 
 an upper insulative material directly below the conductive material between the immediately-longitudinally-adjacent conductive vias; 
 doped or undoped semiconductor material directly below the upper insulative material between the immediately-longitudinally-adjacent conductive vias; and 
 a lower insulative material directly below the semiconductor material between the immediately-longitudinally-adjacent conductive vias. 
 
 
     
     
       2. The construction of  claim 1  wherein the semiconductor material is nowhere directly against the conductive material and is nowhere directly against any of the conductive vias. 
     
     
       3. The construction of  claim 1  wherein the semiconductor material is nowhere directly against any material that is conductive. 
     
     
       4. The construction of  claim 1  wherein the semiconductor material is undoped. 
     
     
       5. The construction of  claim 4  wherein the semiconductor material is devoid of conductivity-modifying impurity. 
     
     
       6. The construction of  claim 1  wherein the semiconductor material is doped. 
     
     
       7. The construction of  claim 6  wherein the semiconductor material is semiconductively doped. 
     
     
       8. The construction of  claim 6  wherein the semiconductor material is conductively doped. 
     
     
       9. The construction of  claim 1  wherein the semiconductor material comprises both doped and undoped portions. 
     
     
       10. The construction of  claim 1  wherein the conductive material predominately comprises metal material and the semiconductor material predominately comprises a combination of polysilicon and conductivity-modifying dopant. 
     
     
       11. The construction of  claim 10  wherein the conductive vias predominately comprise conductively-doped polysilicon. 
     
     
       12. The construction of  claim 1  wherein the conductive material is directly against a top surface of the upper insulative material, the upper insulative material is directly against a top surface of the semiconductor material, and the semiconductor material is directly against a top surface of the lower insulative material. 
     
     
       13. The construction of  claim 1  wherein the conductive vias and the upper insulative material have respective planar top surfaces that are coplanar. 
     
     
       14. The construction of  claim 1  wherein the upper and lower insulative materials are of the same composition relative one another. 
     
     
       15. The construction of  claim 14  comprising insulator material of a composition different from that of the insulative material, the insulator material being longitudinally between (a) and (b) along the conductive line structure, where:
 (a): the upper insulative material, the semiconductor material, and the lower insulative material; and 
 (b): the conductive vias. 
 
     
     
       16. The construction of  claim 1  wherein the conductive line structure comprises a digitline of memory circuitry. 
     
     
       17. The construction of  claim 16  wherein the memory circuitry comprises DRAM. 
     
     
       18. A DRAM construction comprising:
 pairs of recessed access devices, the recessed access devices individually comprising:
 a conductive gate in a trench in semiconductive material; 
 a gate insulator along sidewalls and a base of the trench between the conductive gate and the semiconductive material; 
 a pair of source/drain regions in upper portions of the semiconductive material on opposing sides of the trench; 
 a channel region in the semiconductive material below the pair of source/drain regions along the trench sidewalls and around the trench base; and 
 one of the source/drain regions of the pair of source/drain regions in individual of the pairs of recessed access devices being laterally between the conductive gates in and being shared by the individual pairs of recessed access devices, the others of the source/drain regions of the pair of source/drain regions not being shared in the individual pairs of recessed access devices; 
 
 a digitline structure directly electrically coupled to the one shared source/drain region of multiple of the individual pairs of recessed access devices; 
 a pair of capacitors individually directly electrically coupled to one of the other source/drain regions in the individual pairs of recessed access devices; and 
 elevationally-extending conductive vias spaced longitudinally along the digitline structure, the conductive vias individually directly electrically coupling the digitline line structure to individual of the shared source/drain regions of the individual pairs of recessed access devices, the conductive line structure comprising:
 conductive material directly electrically coupled to the conductive vias and extending between immediately-longitudinally-adjacent of the conductive vias; 
 an upper insulative material directly below the conductive material between the immediately-longitudinally-adjacent conductive vias; 
 doped or undoped semiconductor material directly below the upper insulative material between the immediately-longitudinally-adjacent conductive vias; and 
 a lower insulative material directly below the semiconductor material between the immediately-longitudinally-adjacent conductive vias. 
 
 
     
     
       19. A method used in forming an integrated circuitry construction, comprising:
 providing a substrate comprising conductive nodes, a lower insulative material directly above the conductive nodes, doped or undoped semiconductor material directly above the lower insulative material, and an upper insulative material directly above the semiconductor material; 
 forming contact openings through the upper insulative material, the semiconductor material, and the lower insulative material; the contact openings individually extending to individual of the conductive nodes; 
 forming conductor material in the contact openings that is directly against the individual conductive nodes; 
 forming conductive material directly above the upper insulative material and the conductor material, the conductive material being directly against the conductor material; 
 patterning the conductive material, the upper insulative material, the semiconductor material, and the lower insulative material to form a conductive line structure above the conductive nodes; 
 elevationally-extending conductive vias being spaced longitudinally along the conductive line structure, the conductive vias comprising the conductor material and individually directly electrically coupling the conductive line structure to the individual conductive nodes, the conductive line structure being formed to comprise:
 the conductive material directly electrically coupled to the conductive vias and extending between immediately-longitudinally-adjacent of the conductive vias; 
 the upper insulative material directly below the upper conductive material between the immediately-longitudinally-adjacent conductive vias; 
 the semiconductor material directly below the upper insulative material between the immediately-longitudinally-adjacent conductive vias; and 
 the lower insulative material directly below the semiconductor material between the immediately-longitudinally-adjacent conductive vias. 
 
 
     
     
       20. The method of  claim 19  comprising lining sidewalls of the contact openings with insulator material before forming the conductor material in the contact openings. 
     
     
       21. The method of  claim 19  wherein the semiconductor material is nowhere directly against the conductive material and is nowhere directly against any of the conductive vias. 
     
     
       22. The method of  claim 19  comprising after forming the conductor material in the contact openings, patterning the conductor material to reduce its width within individual of the contact openings. 
     
     
       23. The method of  claim 22  wherein the patterning of the conductor material and the patterning of the conductive material, the upper insulative material, the semiconductor material, and the lower insulative material are collectively conducted in a single masking step. 
     
     
       24. The method of  claim 19  wherein the integrated circuitry comprises DRAM, the conductive nodes are source/drain regions of recessed access devices of the DRAM, and the conductive line structure comprises a digitline structure above the recessed access devices. 
     
     
       25. The method of  claim 24  wherein,
 the recessed access devices are formed to comprise pairs of the recessed access devices, the recessed access devices individually comprising:
 a conductive gate in a trench in semiconductive material; 
 a gate insulator along sidewalls and a base of the trench between the conductive gate and the semiconductive material; 
 a pair of source/drain regions in upper portions of the semiconductive material on opposing sides of the trench; 
 a channel region in the semiconductive material below the pair of source/drain regions along the trench sidewalls and around the trench base; and 
 one of the source/drain regions of the pair of source/drain regions in individual of the pairs of recessed access devices being laterally between the conductive gates in and being shared by the individual pairs of recessed access devices, the others of the source/drain regions of the pair of source/drain regions not being shared in the individual pairs of recessed access devices; and 
 
 the conductive gates being formed in the trenches in the semiconductive material before forming the digitline structure.