Semiconductor package with filler particles in a mold compound

Abstract

A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.

What is claimed is: 
     
       1. A semiconductor package, comprising:
 an integrated circuit formed on a semiconductor substrate; 
 a stress buffer layer on and directly contacting the semiconductor substrate; and 
 a mold compound on a surface of the stress buffer layer opposite the integrated circuit; 
 wherein the mold compound comprises a resin, and the resin includes filler particles; and 
 wherein the filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns. 
 
     
     
       2. The semiconductor package of  claim 1 , wherein the largest of the particles has a size between 10 microns and 25 microns. 
     
     
       3. The semiconductor package of  claim 1 , wherein the integrated circuit includes an analog-to-digital converter. 
     
     
       4. The semiconductor package of  claim 1 , wherein the mold compound is on portions of the semiconductor substrate. 
     
     
       5. The semiconductor package of  claim 1 , wherein the mold comprises at least one of polyimide or a silicone-based material. 
     
     
       6. The semiconductor package of  claim 1 , wherein the stress buffer layer has a thickness that is between 1 micrometer and 50 micrometers. 
     
     
       7. A semiconductor package, comprising:
 an integrated circuit formed on a semiconductor substrate; 
 a stress buffer layer on and directly contacting the semiconductor substrate; and 
 a mold compound on a surface of the stress buffer layer opposite the integrated circuit; 
 wherein the mold compound comprises a resin, and the resin includes filler particles; and 
 wherein filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 50 microns. 
 
     
     
       8. The semiconductor package of  claim 7 , wherein the largest of the particles has a size between 5 microns and 32 microns. 
     
     
       9. The semiconductor package of  claim 7 , wherein the largest of the particles has a size between 10 microns and 25 microns. 
     
     
       10. The semiconductor package of  claim 7 , wherein the integrated circuit includes at least one of an amplifier, a voltage reference, a current reference, or a sensor. 
     
     
       11. A semiconductor package, comprising:
 an integrated circuit on a semiconductor substrate, the integrated circuit including at least one capacitor that is sensitive to stress induced by filler particles in a mold compound; 
 a stress buffer layer on and directly contacting a portion of the semiconductor substrate; and 
 the mold compound over a portion of the semiconductor substrate and a portion of the stress buffer layer;
 wherein the mold compound comprises a resin, and the resin includes filler particles; and 
 wherein filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 50 microns. 
 
 
     
     
       12. The semiconductor package of  claim 11 , wherein the largest of the particles has a size between 5 microns and 32 microns. 
     
     
       13. The semiconductor package of  claim 11 , wherein the largest of the particles has a size between 10 microns and 25 microns. 
     
     
       14. The semiconductor package of  claim 11 , wherein the integrated circuit includes at least one of a data converter, an amplifier, a voltage reference, a current reference, or a sensor. 
     
     
       15. The semiconductor package of  claim 11 , wherein the filler particles comprise at least one of silica and alumina. 
     
     
       16. The semiconductor package of  claim 11 , wherein a first portion of the filler particles are spherical and a second portion of the filler particles have shapes that are non-geometric. 
     
     
       17. The semiconductor package of  claim 11 , further comprising a leadframe, wherein the semiconductor substrate is coupled to the leadframe and wherein the mold compound covers the leadframe. 
     
     
       18. A method, comprising:
 forming an integrated circuit on a semiconductor substrate; 
 forming a stress buffer layer on and directly contacting the semiconductor substrate; 
 attaching the semiconductor substrate to leads; and 
 applying a mold compound on a surface of the stress buffer layer opposite the integrated circuit, wherein the mold compound comprises a resin, and the resin includes filler particles, and wherein the filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns. 
 
     
     
       19. The method of  claim 18 , wherein the largest of the filler particles has a size between 10 microns and 25 microns.