NAND flash memory device

Abstract

According to an embodiment, a semiconductor storage device includes a detection circuit configured to detect an error in data read from a first memory cell array. The read data of a size corresponding to a page unit is subjected to detection of an error for each of a plurality of first units into which the page unit is divided. When performing a first operation of concurrently executing outputting of first data read from the first memory cell array to an outside and reading of second data different from the first data from the first memory array, an interface circuit is configured to output information based on the error detected with respect to the first data to the outside.

What is claimed is: 
     
       1. A NAND flash memory device comprising:
 an interface circuit configured to communicate with an outside; 
 a first memory cell array and a second memory cell array, each of which includes a memory cell transistor configured to store data and from each of which data is read for each page unit; 
 a first register configured to store data read from the first memory cell array; 
 a second register configured to store data read from the second memory cell array; and 
 a detection circuit configured to detect an error in data read from the first memory cell array and the second memory cell array, 
 wherein the read data of a size corresponding to the page unit is subjected to detection of an error for each of a plurality of first units into which the page unit is divided, and 
 when performing an operation of outputting the read data, the interface circuit is configured to output information based on the error detected in the read data output during the operation, the operation including at least one of a first operation, a second operation, and a third operation, 
 the first operation concurrently executing:
 outputting first data stored in the first register to the outside; and 
 reading second data different from the first data from the first memory cell array and storing the second data in the first register; 
 
 the second operation concurrently executing:
 outputting the first data stored in the first register to the outside; and 
 outputting third data stored in the second register to the outside; and 
 
 the third operation concurrently executing:
 outputting the first data stored in the first register to the outside; 
 reading the second data from the first memory cell array and storing the second data in the first register; 
 outputting the third data stored in the second register to the outside; and 
 reading fourth data different from the third data from the second memory cell array and storing the fourth data in the second register. 
 
 
     
     
       2. The device of  claim 1 , wherein the information includes one of an error bit count detected for each of the first units and a value indicating whether the error bit count detected for each of the first units exceeds a given threshold and a maximum value of the error bit count detected for each of the first units. 
     
     
       3. The device of  claim 2 , wherein the threshold is configured to be set from the outside. 
     
     
       4. The device of  claim 2 , wherein the threshold includes a fixed value. 
     
     
       5. The device of  claim 2 , wherein
 when performing the first operation, the interface circuit is configured to output the information concerning the first data to the outside upon receiving a first command in the first operation, and output the information concerning the second data to the outside upon receiving a second command after the first operation, 
 when performing the second operation, the interface circuit is configured to output the information concerning the first data and the third data to the outside upon receiving a first command in the second operation, and 
 when performing the third operation, the interface circuit is configured to output the information concerning the first data and the third data to the outside upon receiving a first command in the third operation, and output the information concerning the second data and the fourth data to the outside upon receiving a second command after the third operation. 
 
     
     
       6. The device of  claim 2 , further comprising a table configured to store the information,
 wherein the interface circuit is configured to output the information from the table. 
 
     
     
       7. The device of  claim 6 , wherein the interface circuit is configured to consecutively output the information for each of the first units from the table upon receiving a first command in the operation. 
     
     
       8. The device of  claim 6 , wherein the interface circuit is configured to output, from the table, the error bit count of a portion of the information which corresponds to the first unit, upon receiving a first command in the first operation. 
     
     
       9. The device of  claim 1 , wherein the interface circuit is configured to recognize as a command, an input signal which is different from an asserted chip select signal and is received immediately after reception of the chip select signal. 
     
     
       10. The device of  claim 1 , wherein the interface circuit is configured to recognize, as a command, an input signal received during reception of an asserted command latch enable signal.