Memory system and SoC including linear remapper and access window

Abstract

A system on chip which is connected with a plurality of memory chips includes first and second processors, a first access window, a first linear remapper, and a memory controller. The first and second processors are configured to provide an address for using the plurality of memory chips. The first access window sets an area, accessed only by the first processor, from among address areas of one or more of the plurality of memory chips. The first linear remapper remaps an address received from the first processor. The memory controller performs a partial linear access operation with respect to the plurality of memory chips, based on an area set by the first access window and an address remapped by the first linear remapper.

What is claimed is: 
     
       1. A memory system comprising:
 a plurality of memory chips; and 
 a system on chip connected with the plurality of memory chips, wherein: 
 the system on chip includes:
 first and second processors configured to provide an address for using the plurality of memory chips; 
 a first access window configured to set an area, accessed only by the first processor, from among address areas of one or more of the plurality of memory chips; 
 a first linear remapper configured to generate a linear-access memory map from addresses within the area that are received from the first processor; and 
 a memory controller configured to control a partial linear access operation with respect to the plurality of memory chips, based on the area set by the first access window and the linear-access memory map, wherein: 
 
 the first linear remapper generates the linear-access memory map by remapping, for each of the memory chips, consecutively increasing memory addresses of the memory chip, within an interleaved-access memory map, to monotonically increasing memory addresses for accessing a first of the memory chips, 
 the memory controller applies the partial linear access operation to the first memory chip so as to sequentially access consecutive memory addresses of the first memory chip within the linear-access memory map, and 
 each of any two consecutive memory addresses within the interleaved-access memory map addresses a different one of the memory chips. 
 
     
     
       2. The memory system of  claim 1 , further comprising:
 a second access window configured to set an area, accessed only by the second processor, from among address areas of one or more of the plurality of memory chips; and 
 a second linear remapper configured to remap an address received from the second processor and to provide an address thus remapped to the memory controller, wherein 
 the memory controller performs a partial linear access operation with respect to the plurality of memory chips, based on the area set by the second access window and the address remapped by the second linear remapper. 
 
     
     
       3. The memory system of  claim 2 , wherein the partial linear access operation is performed even though at least one of the plurality of memory chips has an asymmetric memory configuration including a non-accessible area. 
     
     
       4. The memory system of  claim 3 , wherein the first or second access window sets the non-accessible area. 
     
     
       5. The memory system of  claim 4 , wherein:
 the first access window receives a first CONFIG signal from a special function register (SFR) and sets an independent access area that only the first processor accesses, and 
 the first linear remapper receives a second CONFIG signal from the SFR and selectively performs an interleaving access operation or a linear access operation with respect to the plurality of memory chips. 
 
     
     
       6. The memory system of  claim 2 , wherein:
 the first processor is a modem processor, and 
 the first and second processors, the memory controller, the first and second access windows, and the first and second linear remappers are implemented on the system on chip. 
 
     
     
       7. The memory system of  claim 2 , wherein:
 the first access window receives a first CONFIG signal from a special function register (SFR) and sets an independent access area that only the first processor accesses, and 
 the first linear remapper receives a second CONFIG signal from the SFR and selectively performs an interleaving access operation or a linear access operation with respect to the plurality of memory chips. 
 
     
     
       8. A mobile electronic device comprising:
 a display panel configured to display image data; 
 an RF transceiver unit configured to perform wireless data communications; 
 a plurality of memory chips configured to store data; and 
 an application processor connected to the display panel, the RF transceiver unit, and the plurality of memory chips, wherein: 
 the application processor includes:
 first and second processors configured to provide an address for using the plurality of memory chips; 
 a first access window configured to set an area, accessed only by the first processor, from among address areas of one or more of the plurality of memory chips; 
 a first linear remapper configured to generate a linear-access memory map from addresses within the area that are received from the first processor; and 
 a memory controller configured to perform a partial linear access operation with respect to the plurality of memory chips, based on the area set by the first access window and the linear-access memory map, wherein: 
 
 the first linear remapper generates the linear-access memory map by remapping, for each of the memory chips, consecutively increasing memory addresses of the memory chip, within an interleaved-access memory map, to monotonically increasing memory addresses for accessing a first of the memory chips, 
 the memory controller applies the partial linear access operation to the first memory chip so as to sequentially access consecutive memory addresses of the first memory chip within the linear-access memory map, and 
 each of any two consecutive memory addresses within the interleaved-access memory map addresses a different one of the memory chips. 
 
     
     
       9. The mobile electronic device of  claim 8 , wherein the application processor further includes:
 a second access window configured to set an area, accessed only by the second processor, from among address areas of one or more of the plurality of memory chips; and 
 a second linear remapper configured to remap an address received from the second processor and to provide an address thus remapped to the memory controller, wherein 
 the memory controller performs a partial linear access operation with respect to the plurality of memory chips, based on the area set by the second access window and the address remapped by the second linear remapper. 
 
     
     
       10. A method of accessing memory chips, the method comprising:
 accessing, with a first processor, a first memory area within each of the memory chips through an interleaved access operation; 
 generating a linear-access memory map by remapping, for each of the memory chips, consecutively increasing memory addresses of the memory chip, within an interleaved-access memory map, to monotonically increasing memory addresses for accessing a second memory area within a first of the memory chips through a linear access operation; and 
 accessing, solely with a second processor, the second memory area within the first memory chip solely through the linear access operation so as to sequentially access consecutive memory addresses of the first memory chip within the linear-access memory map, wherein: 
 each of any two consecutive memory addresses within the interleaved-access memory map addresses a different one of the memory chips, and 
 the second memory area is a same size or larger than the first memory area. 
 
     
     
       11. The method of  claim 10 , further comprising accessing, with the second processor, a third memory area, within each of the memory chips through the interleaved access operation. 
     
     
       12. The method of  claim 10 , further comprising:
 accessing, with the first processor, a third memory area within a second of the memory chips, different from the first memory chip, using the linear access operation, wherein 
 the third memory area is a same size or larger than the first memory area. 
 
     
     
       13. The method of  claim 10 , wherein if a memory region to be accessed by the second processor exceeds a size of the second memory area, the second processor accesses the second memory area within the first memory chip through the linear access operation and accesses a third memory area of a second of the memory chips, differing from the first memory chip, through the linear access operation. 
     
     
       14. The method of  claim 10 , wherein:
 the second processor accesses the second memory area but the first processor does not, and 
 both the first and second processors access the first memory area. 
 
     
     
       15. A memory system that accesses memory chips, the system comprising:
 a first processor that accesses a first memory area within each of the memory chips through an interleaved access operation; 
 a linear remapping component that generates a linear-access memory map by remapping, for each of the memory chips, consecutively increasing memory addresses of the memory chip, within an interleaved-access memory map, to monotonically increasing memory addresses for accessing a second memory area within a first of the memory chips through a linear access operation; and 
 a second processor that solely accesses the second memory area within the first memory chip solely through the linear access operation so as to sequentially access consecutive memory addresses of the first memory chip within the linear-access memory map, wherein: 
 each of any two consecutive memory addresses within the interleaved-access memory map addresses a different one of the memory chips, and 
 the second memory area is a same size or larger than the first memory area. 
 
     
     
       16. The memory system of  claim 15 , wherein the second processor accesses a third memory area within each of the memory chips through the interleaved access operation. 
     
     
       17. The memory system of  claim 15 , wherein:
 the first processor accesses a third memory area within a second of the memory chips, different from the first memory chip, using the linear access operation, and 
 the third memory area is a same size or larger than the first memory area. 
 
     
     
       18. The memory system of  claim 15 , wherein:
 the second processor accesses the second memory area but the first processor does not, and 
 both the first and second processors access the first memory area.