Circuit device, electronic device, and cable harness

Abstract

A circuit device includes first and second physical layer circuits, a bus switch circuit that switches connection between a first bus and a second bus that comply with a USB standard, on in a first period and off in a second period, and a processing circuit that performs, in the second period, processing for transferring packets on a transfer route that includes the first bus, the first and second physical layer circuits, and the second bus. When a host chirp K/J is detected on the first bus by the first physical layer circuit, the second physical layer circuit outputs a host chirp K/J to the second bus in the state where connection between the first bus and the second bus is switched off by the bus switch circuit.

What is claimed is: 
     
       1. A circuit device comprising:
 a first physical layer circuit to which a first bus that complies with a USB standard is connected; 
 a second physical layer circuit to which a second bus that complies with the USB standard is connected; 
 a bus switch circuit, one end of which is connected to the first bus, another end of which is connected to the second bus, and that switches connection between the first bus and the second bus on in a first period and off in a second period; and 
 a processing circuit that performs, in the second period, transfer processing for transmitting a packet received from the first bus via the first physical layer circuit, to the second bus via the second physical layer circuit, and transmitting a packet received from the second bus via the second physical layer circuit, to the first bus via the first physical layer circuit, 
 wherein, when a host chirp K/J is detected on the first bus by the first physical layer circuit, the second physical layer circuit outputs a host chirp K/J to the second bus in a state where connection between the first bus and the second bus is switched off by the bus switch circuit. 
 
     
     
       2. The circuit device according to  claim 1 ,
 wherein, in a case where HS termination is detected on the second bus by the second physical layer circuit, the first physical layer circuit switches on HS termination of the first physical layer circuit. 
 
     
     
       3. The circuit device according to  claim 2 ,
 wherein the first physical layer circuit detects the host chirp K/J on the first bus in a state where the HS termination of the first physical layer circuit is off, and in a case where the HS termination is detected on the second bus by the second physical layer circuit, switches on the HS termination of the first physical layer circuit. 
 
     
     
       4. The circuit device according to  claim 1 ,
 wherein, when a device chirp K is detected on the second bus, the first physical layer circuit outputs a device chirp K to the first bus in a state where connection between the first bus and the second bus is switched off by the bus switch circuit. 
 
     
     
       5. The circuit device according to  claim 4 , further comprising:
 a detection circuit that performs current detection in the bus switch circuit, 
 wherein, when the detection circuit detects flow of a current from the second bus to the first bus via the bus switch circuit after USB bus reset, the first physical layer circuit outputs the device chirp K to the first bus. 
 
     
     
       6. The circuit device according to  claim 5 ,
 wherein, when the detection circuit detects flow of a current from the second bus to the first bus via the bus switch circuit, the bus switch circuit switches connection between the first bus and the second bus from on to off, and the second physical layer circuit switches on HS termination of the second physical layer circuit. 
 
     
     
       7. The circuit device according to  claim 5 ,
 wherein, when a current flows from the second bus to the first bus via the bus switch circuit after the bus reset, the detection circuit detects that the first bus is a bus on an upstream side and the second bus is a bus on a downstream side, and when a current flows from the first bus to the second bus via the bus switch circuit after the bus reset, detects that the first bus is a bus on a downstream side and the second bus is a bus on an upstream side. 
 
     
     
       8. The circuit device according to  claim 4 ,
 wherein, when stop of output of the device chirp K is detected on the second bus, the first physical layer circuit stops outputting the device chirp K to the first bus. 
 
     
     
       9. The circuit device according to  claim 8 ,
 wherein, when the host chirp K/J is detected on the first bus by the first physical layer circuit after stop of the device chirp K on the second bus, the second physical layer circuit outputs the host chirp K/J to the second bus. 
 
     
     
       10. A circuit device comprising:
 a first physical layer circuit to which a first bus that complies with a USB standard is connected; 
 a second physical layer circuit to which a second bus that complies with the USB standard is connected; 
 a bus switch circuit, one end of which is connected to the first bus, another end of which is connected to the second bus, and that switches connection between the first bus and the second bus on in a first period and off in a second period; 
 a processing circuit that performs, in the second period, transfer processing for transmitting a packet received from the first bus via the first physical layer circuit, to the second bus via the second physical layer circuit, and transmitting a packet received from the second bus via the second physical layer circuit, to the first bus via the first physical layer circuit; and 
 a detection circuit that detects that the first bus is a bus on an upstream side and the second bus is a bus on a downstream side, when a current flows from the second bus to the first bus via the bus switch circuit after USB bus reset, and detects that the first bus is a bus on a downstream side and the second bus is a bus on an upstream side, when a current flows from the first bus to the second bus via the bus switch circuit after the bus reset. 
 
     
     
       11. The circuit device according to  claim 10 ,
 wherein, when the detection circuit detects flow of a current from the second bus to the first bus via the bus switch circuit after the bus reset, the first physical layer circuit outputs a device chirp K to the first bus. 
 
     
     
       12. The circuit device according to  claim 11 ,
 wherein, when a host chirp K/J is detected on the first bus by the first physical layer circuit, the second physical layer circuit outputs a host chirp K/J to the second bus. 
 
     
     
       13. An electronic device comprising:
 the circuit device according to  claim 1 ; and 
 a processing device that is connected to the first bus. 
 
     
     
       14. A cable harness comprising:
 the circuit device according to  claim 1 ; and 
 a cable.