Integrated circuit, and method and system for providing power to integrated circuit

Abstract

An integrated circuit includes a highest class core circuit that has a positive power supply terminal connected to a positive power supply terminal of an external power source, and is configured to receive a first supply voltage which is at least a portion of a an input supply voltage that is provided from the external power source based on an operation throughput; and a lowest class core circuit that has a positive power supply terminal connected to a negative power supply terminal of an adjacent upper class core circuit, has a negative power supply terminal connected to a negative power supply terminal of the external power source, and is configured to receive a second supply voltage which is at least a portion of a part of the input supply voltage that excludes the first supply voltage.

What is claimed is: 
     
       1. An integrated circuit comprising:
 a highest class core circuit that has a positive power supply terminal connected to a positive power supply terminal of an external power source, and is configured to receive a first supply voltage which is at least a portion of a an input supply voltage that is provided from the external power source based on an operation throughput; 
 a lowest class core circuit that has a positive power supply terminal connected to a negative power supply terminal of an adjacent upper class core circuit, has a negative power supply terminal connected to a negative power supply terminal of the external power source, and is configured to receive a second supply voltage which is at least a portion of a part of the input supply voltage that excludes the first supply voltage; 
 a first switch that connects the positive power supply terminal of the highest class core circuit to the negative power supply terminal of the highest class core circuit; and 
 a second switch that connects the positive power supply terminal of the lowest class core circuit to the negative power supply terminal of the lowest class core circuit, 
 wherein opening and closing of the first switch and the second switch are determined based on an operation throughput of each of the highest class core circuit and the lowest class core circuit, and 
 wherein a distribution ratio between the first supply voltage and the second supply voltage from the input supply voltage is determined based on the operation throughput of each of the highest class core circuit and the lowest class core circuit. 
 
     
     
       2. The integrated circuit of  claim 1 , wherein the adjacent upper class core circuit of the lowest class core circuit is the highest class core circuit. 
     
     
       3. The integrated circuit of  claim 2 , wherein the highest class core circuit and the lowest class core circuit are configured such that the operation throughput of each of the highest class core circuit and the lowest class core circuit depends on a change frequency of an input signal that is received by each of the highest class core circuit and the lowest class core circuit. 
     
     
       4. The integrated circuit of  claim 3 , wherein the highest class core circuit and the lowest class core circuit are configured such that the operation throughput of each of the highest class core circuit and the lowest class core circuit increases as the change frequency of the input signal that is received by each of the highest class core circuit and the lowest class core circuit increases. 
     
     
       5. The integrated circuit of  claim 1 , further comprising:
 a third core circuit that has a positive power supply terminal connected to the negative power supply terminal of the highest class core circuit, and is configured to receive a third supply voltage which is at least a portion of the part of the input supply voltage that excludes the first supply voltage and the second supply voltage. 
 
     
     
       6. The integrated circuit of  claim 5 , wherein a distribution ratio between the first supply voltage, the second supply voltage, and the third supply voltage from the input supply voltage is determined based on an operation throughput of each of the highest class core circuit, the lowest class core circuit, and the third core circuit. 
     
     
       7. The integrated circuit of  claim 1 , further comprising:
 a core circuit that has a positive power supply terminal connected to a positive power supply terminal of a fourth core circuit belonging to an upper class than the lowest class core circuit, has a negative power supply terminal connected to a fifth core circuit belonging to a lower class than the fourth core circuit, and is configured to receive at least a portion of the part of the input supply voltage that excludes the first supply voltage and the second supply voltage. 
 
     
     
       8. The integrated circuit of  claim 7 , wherein at least one of the fourth core circuit and the fifth core circuit is a middle class core circuit that is different from the highest class core circuit and the lowest class core circuit. 
     
     
       9. The integrated circuit of  claim 7 , wherein the fourth core circuit is the highest class core circuit, and the fifth core circuit is the lowest class core circuit. 
     
     
       10. A method of distributing and providing an input supply voltage that is provided from a power source to an integrated circuit including at least a highest class core circuit and a lowest class core circuit, the method comprising:
 determining an operation throughput of each of the highest class core circuit and the lowest core circuit; 
 determining, based on the operation throughput, a distribution ratio between a first supply voltage and a second supply voltage from the input supply voltage 
 providing, based on the determined distribution ratio, the first supply voltage which is at least a portion of the input supply voltage to the highest class core circuit; and 
 providing the second supply voltage which is at least a portion of a part of the input supply voltage that excludes the first supply voltage to the lowest class core circuit, 
 wherein the integrated circuit further comprises a first switch that connects a positive power supply terminal of the highest class core circuit to a negative power supply terminal of the highest class core circuit, and a second switch that connects a positive power supply terminal of the lowest class core circuit to a negative power supply terminal of the lowest class core circuit, and 
 wherein opening and closing of the first switch and the second switch are determined based on an operation throughput of each of the highest class core circuit and the lowest class core circuit. 
 
     
     
       11. The method of  claim 10 , wherein the operation throughput of each of the highest class core circuit and the lowest class core circuit depends on a change frequency of an input signal that is received by each of the highest class core circuit and the lowest class core circuit. 
     
     
       12. The method of  claim 10 , further comprising:
 adjusting, based on whether an operation throughput of the highest class core circuit changes, the first supply voltage that is provided to the highest class core circuit. 
 
     
     
       13. The method of  claim 12 , wherein the adjusting of the first supply voltage comprises decreasing the first supply voltage as the operation throughput of the highest class core circuit increases. 
     
     
       14. A system for providing power to an integrated circuit, the system comprising:
 a power source that provides an input supply voltage to the integrated circuit through a positive power supply terminal and a negative power supply terminal; 
 a highest class core circuit that has a positive power supply terminal connected to the positive power supply terminal of the power source, and is configured to receive a first supply voltage which is at least a portion of the input supply voltage based on an operation throughput; and 
 a lowest class core circuit that has a positive power supply terminal connected to a negative power supply terminal of an adjacent upper class core circuit, has a negative power supply terminal connected to the negative power supply terminal of the power source, and is configured to receive a second supply voltage which is at least a portion of a part of the input supply voltage that excludes the first supply voltage from the input supply voltage; 
 a first switch that connects the positive power supply terminal of the highest class core circuit to the negative power supply terminal of the highest class core circuit; and 
 a second switch that connects the positive power supply terminal of the lowest class core circuit to the negative power supply terminal of the lowest class core circuit, 
 wherein opening and closing of the first switch and the second switch are determined based on an operation throughput of each of the highest class core circuit and the lowest class core circuit, and 
 wherein a distribution ratio between the first supply voltage and the second supply voltage from the input supply voltage is determined based on the operation throughput of each of the highest class core circuit and the lowest class core circuit. 
 
     
     
       15. The system of  claim 14 , wherein the highest class core circuit and the lowest class core circuit are configured such that the operation throughput of each of the highest class core circuit and the lowest class core circuit depends on change frequencies of input signals that are received by each of the highest class core circuit and the lowest class core circuit, respectively. 
     
     
       16. The system of  claim 15 , wherein the highest class core circuit and the lowest class core circuit are configured such that,
 the operation throughput of the highest class core circuit increases as the change frequency of the input signal that is received by the highest class core circuit increases, and 
 the operation throughput of the lowest class core circuit increases as the change frequency of the input signal that is received by the lowest class core circuit increases.