Ferroelectric memory device and method of manufacturing the same

Abstract

A ferroelectric memory device according to an embodiment of the present disclosure includes a substrate, a ferroelectric material layer disposed on the substrate, a gate electrode layer disposed on the ferroelectric material layer, and a polarization switching seed layer disposed between the ferroelectric material layer and the gate electrode layer.

What is claimed is: 
     
       1. A ferroelectric memory device comprising:
 a substrate; 
 a ferroelectric material layer disposed on the substrate; 
 a gate electrode layer disposed on the ferroelectric material layer; and 
 a polarization switching seed layer disposed between the ferroelectric material layer and the gate electrode layer, 
 wherein the polarization switching seed layer is a layer pattern with a predetermined cross-sectional area. 
 
     
     
       2. The ferroelectric memory device of  claim 1 , wherein the polarization switching seed layer is in contact with a portion of the ferroelectric material layer. 
     
     
       3. The ferroelectric memory device of  claim 1 , wherein the polarization switching seed layer comprises a conductive material. 
     
     
       4. The ferroelectric memory device of  claim 3 , wherein the polarization switching seed layer comprises at least one selected from the group consisting of tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), platinum (Pt), iridium (Ir), ruthenium (Ru), tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide. 
     
     
       5. The ferroelectric memory device of  claim 1 , wherein the polarization switching seed layer has a cross-sectional area with a length and a width each measuring about 2 nm to about 10 nm. 
     
     
       6. The ferroelectric memory device of  claim 1 , wherein the ferroelectric material layer comprises at least one of hafnium oxide, zirconium oxide, and hafnium zirconium oxide. 
     
     
       7. The ferroelectric memory device of  claim 1 , further comprising:
 a source region and a drain region disposed in the substrate at both ends of the gate electrode layer. 
 
     
     
       8. A ferroelectric memory device comprising:
 a substrate; 
 a ferroelectric material layer disposed on the substrate; 
 a gate electrode layer disposed on the ferroelectric material layer; and 
 a polarization switching seed layer disposed between the ferroelectric material layer and the gate electrode layer, 
 wherein the polarization switching seed layer comprises a resistance change material layer including a conductive filament being formed in the resistance change material layer. 
 
     
     
       9. The ferroelectric memory device of  claim 8 , wherein the conductive filament has a diameter of about 2 nm to about 10 nm. 
     
     
       10. A ferroelectric memory device comprising:
 a substrate including a channel structure having a bottom surface and side surfaces; 
 a ferroelectric material layer disposed on the bottom surface and the side surfaces of the channel structure; 
 a polarization switching seed layer pattern and an insulating layer pattern on the ferroelectric material layer, the polarization switching seed layer pattern and the insulating layer pattern alternately stacked along the side surfaces of the channel structure; and 
 a gate electrode layer electrically connected to the polarization switching seed layer pattern in the channel structure. 
 
     
     
       11. The ferroelectric memory device of  claim 10 , wherein the polarization switching seed layer pattern comprises at least one selected from the group consisting of tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), platinum (Pt), iridium (Ir), ruthenium (Ru), tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide. 
     
     
       12. The ferroelectric memory device of  claim 10 , wherein the insulating layer pattern comprises at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxide. 
     
     
       13. The ferroelectric memory device of  claim 10 , wherein the polarization switching seed layer pattern is a layer pattern of with a predetermined cross-sectional area on the ferroelectric material layer. 
     
     
       14. The ferroelectric memory device of  claim 13 , wherein the polarization switching seed layer has a cross-sectional area with a length and a width each measuring about 2 nm to about 10 nm.