On-die resistor measurement

Abstract

Examples herein describe a die that includes a testing system (e.g., testing circuitry) for measuring the actual resistance of on-die resistors. When testing the die, an I/O element (e.g., a solder bump) can be used to sweep a voltage across the on-die resistor. The testing system identifies when the voltage across the on-die resistor reaches a predefined reference voltage and measures the corresponding current. Using the measured current and the reference voltage, the testing system can identify the actual resistance of the on-die resistor. In one embodiment, the on-die resistor is tunable such if the on-die resistor has a divergent value, the die can adjust its resistance value to the desired value.

What is claimed is: 
     
       1. A method for measuring a resistance value of an on-die resistor, comprising:
 incrementing a voltage at an I/O element of a semiconductor die using a testing application coupled to the I/O element, wherein the I/O element is electrically coupled to a first side of the on-die resistor in the semiconductor die and the testing application is external to the semiconductor die; 
 monitoring an output of a comparator in the semiconductor die, wherein a first input of the comparator is coupled to the first side of the on-die resistor and a second input of the comparator is coupled to a reference voltage; 
 measuring a current flowing through the I/O element in response to the output of the comparator switching from a first value to a second value; and 
 determining the resistance value of the on-die resistor based on the measured current and the reference voltage. 
 
     
     
       2. The method of  claim 1 , wherein incrementing the voltage at the I/O element comprises:
 sweeping the voltage on the I/O element until the output of the comparator switches from the first value to the second value. 
 
     
     
       3. The method of  claim 1 , wherein a second end of the on-die resistor is coupled to ground, wherein a voltage across the on-die resistor is the same as the reference voltage when the output of the comparator switches from the first value to the second value. 
     
     
       4. The method of  claim 1 , wherein the I/O element is coupled to the on-die resistor via an electrical path in the semiconductor die having an associated parasitic resistance, wherein the method comprises:
 subtracting the voltage at the I/O element from the reference voltage to identify the voltage across the parasitic resistance; and 
 determining a resistance value of the parasitic resistance based on the voltage across the parasitic resistance and the measured current. 
 
     
     
       5. The method of  claim 1 , wherein determining the resistance value of the on-die resistor comprises:
 dividing the reference voltage by the measured current. 
 
     
     
       6. The method of  claim 1 , further comprising:
 upon determining the resistance value of the on-die resistor does not match a desired resistance, adjusting the resistance value of the on-die resistor to match the desired resistance. 
 
     
     
       7. The method of  claim 6 , further comprising:
 calibrating a memory driver in the semiconductor die using the on-die resistor after the on-die resistor has been adjusted to match the desired resistance. 
 
     
     
       8. A system comprising:
 a die comprising an on-die resistor; 
 a testing application coupled to the die, wherein the testing application is configured to:
 increment a voltage at an I/O element of the die, wherein the I/O element is electrically coupled to a first side of the on-die resistor in the die; 
 monitor an output of a comparator in the die, wherein a first input of the comparator is coupled to the first side of the on-die resistor and a second input of the comparator is coupled to a reference voltage; 
 measure a current flowing through the I/O element in response to the output of the comparator switching from a first value to a second value; and 
 determine a resistance value of the on-die resistor based on the measured current and the reference voltage. 
 
 
     
     
       9. The system of  claim 8 , wherein incrementing the voltage at the I/O element comprises:
 sweeping the voltage on the I/O element until the output of the comparator switches from the first value to the second value. 
 
     
     
       10. The system of  claim 8 , wherein a second end of the on-die resistor is coupled to ground, wherein a voltage across the on-die resistor is the same as the reference voltage when the output of the comparator switches from the first value to the second value. 
     
     
       11. The system of  claim 8 , wherein the I/O element is coupled to the on-die resistor via an electrical path in the die having an associated parasitic resistance, wherein the testing application is configured to:
 subtract the voltage at the I/O element from the reference voltage to identify the voltage across the parasitic resistance; and 
 determine a resistance value of the parasitic resistance based on the voltage across the parasitic resistance and the measured current. 
 
     
     
       12. The system of  claim 8 , wherein the testing application is configured to:
 upon determining the resistance value of the on-die resistor does not match a desired resistance, adjust the resistance value of the on-die resistor to match the desired resistance. 
 
     
     
       13. The system of  claim 12 , wherein the testing application is configured to:
 calibrate a memory driver in the die using the on-die resistor after the on-die resistor has been adjusted to match the desired resistance. 
 
     
     
       14. A semiconductor die, comprising:
 an on-die resistor; 
 an I/O element coupled to a first end of the on-die resistor; and 
 a comparator, wherein a first input of the comparator is coupled to the first end of the on-die resistor and a second input of the comparator is coupled to a reference voltage, 
 wherein an output of the comparator is configured to switch from a first value to a second value when a voltage across the on-die resistor matches the reference voltage; and 
 an adjustment circuit configured to adjust a resistance value of the on-die resistor to match a desired value based on the output of the comparator. 
 
     
     
       15. The semiconductor die of  claim 14 , wherein the I/O element is a solder bump and wherein the semiconductor die further comprises:
 an electrical path coupling the solder bump to on-die resistor, wherein a parasitic resistance associated with the electrical path results in the voltage driven onto the solder bump being different from the voltage at the first end of the on-die resistor. 
 
     
     
       16. The semiconductor die of  claim 14 , wherein a second end of the on-die resistor is coupled to ground, wherein, when driving a voltage onto the I/O element, a current through the I/O element is the same as the current flowing through the on-die resistor. 
     
     
       17. The semiconductor die of  claim 14 , wherein the adjustment circuit adjusts the resistance value based on an external testing application or an internal calibration circuit. 
     
     
       18. The semiconductor die of  claim 14 , further comprising:
 a memory driver coupled to the on-die resistor, wherein the on-die resistor is a calibration resistor for calibrating the memory driver. 
 
     
     
       19. The semiconductor die of  claim 18 , wherein the memory driver is configured to transmit data signals to a high-bandwidth memory after being calibrated using the on-die resistor. 
     
     
       20. The semiconductor die of  claim 14 , wherein the semiconductor die is a field programmable gate array (FPGA), wherein the output of the comparator is coupled to an FPGA fabric.