Systems and methods for digital synthesis of output signals using resonators

Abstract

Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.

What is claimed is: 
     
       1. A direct frequency synthesizer comprising:
 a high speed resonator that generates a frequency signal; 
 an oscillator that receives the frequency signal and generates an output signal; 
 a clock generator that receives the output signal of the oscillator and generates a clock signal from the output signal; 
 a controller that generates a frequency control word describing a desired output digital signal; and 
 a direct digital frequency synthesizer that receives the clock signal and the frequency control word and generates a desired digital output signal based on the clock signal and frequency control word; and 
 a high speed digital to analog converter that receives the output signal from the oscillator and the desired digital output signal from the direct digital frequency synthesizer and outputs an analog signal based on the desired digital output signal. 
 
     
     
       2. The direct frequency synthesizer of  claim 1  further comprising:
 frequency compensation circuitry that generates a frequency compensation value to adjust for errors in the frequency signal generated by the high speed resonator and adds the frequency compensation value to the frequency control word. 
 
     
     
       3. The direct frequency synthesizer of  claim 2  wherein the frequency compensation circuitry comprises:
 a temperature sensor that measure an operating temperature; and 
 wherein the frequency compensation circuitry uses the operating temperature to calculate a correct amplitude value for particular time period to adjust the frequency compensation value. 
 
     
     
       4. The direct frequency synthesizer of  claim 2  wherein the frequency compensation circuitry comprises:
 frequency offset correction circuitry that accounts for resonant frequency offsets in the frequency signal generated by the high speed resonator due to properties of the resonator and provides frequency offset information to the frequency compensation circuitry to generate the frequency compensation value. 
 
     
     
       5. The direct frequency synthesizer of  claim 2  wherein the frequency compensation circuitry comprises a non-volatile memory that stores different output signals that may be generated using the direct digital synthesizer that is used in generating the frequency compensation value. 
     
     
       6. The direct frequency synthesizer of  claim 2  wherein the non-volatile memory outputs an initial frequency error, process information, and a preset frequency to the frequency compensation circuitry. 
     
     
       7. The direct frequency synthesizer of  claim 2  wherein the frequency compensation frequency circuitry comprises:
 an analog to digital converter that receives the clock signal from the clock generator and a voltage controlled oscillator signal and generates a frequency adjustment value based on the voltage control oscillator signal, Wherein the frequency adjustment value is used to generate the frequency compensation value. 
 
     
     
       8. The direct frequency synthesizer of  claim 1  wherein the high speed resonator is a resonator selected from the group consisting of a bulk acoustic wave (BAW) resonator, a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR). 
     
     
       9. A method for generating a signal from a high speed resonator comprising:
 generating a frequency signal using a high speed resonator 
 receiving the frequency signal in an oscillator; 
 generating an output signal from the frequency signal using the oscillator; 
 receiving the output signal of the oscillator in a clock generator; 
 generating a clock signal from the output signal of the oscillator using the clock generator; 
 generating a frequency control word describing a desired output digital signal using a controller; 
 receiving the clock signal and the frequency control word in a direct digital frequency synthesizer; and 
 generating a desired digital output signal based on the clock signal and frequency control word using the direct digital frequency synthesizer; 
 receiving the output signal from the oscillator and the desired digital output signal from the direct digital frequency synthesizer in a high speed digital to analog converter; and 
 converting the desired digital output signal to an analog output signal. 
 
     
     
       10. The method of  claim 9  further comprising:
 generating a frequency compensation value to adjust for errors in the frequency signal generated by the high speed resonator using frequency compensation circuitry; and 
 adding the frequency compensation value to the frequency control word. 
 
     
     
       11. The method of  claim 10  further comprising:
 measuring an operating temperature using a temperature sensor; and 
 calculating a correct amplitude value for particular time period based on the operating temperature to adjust the frequency compensation value using the frequency compensation circuitry. 
 
     
     
       12. The method of  claim 10  wherein the frequency compensation circuitry comprises:
 accounting for resonant frequency offsets in the frequency signal generated by the high speed resonator due to properties of the resonator and providing frequency offset information representing the resonant frequency offsets to the frequency compensation circuitry to generate the frequency compensation value. 
 
     
     
       13. The method of  claim 10  further comprising storing different output signals that may be generated using the direct digital synthesizer in the nonvolatile memory for use in generating the frequency compensation value. 
     
     
       14. The method of  claim 10  further comprising outputting an initial frequency error, process information, and a preset frequency to the frequency compensation circuitry from the non-volatile memory. 
     
     
       15. The method of  claim 10  further comprising:
 receiving the clock signal from the clock generator and a voltage controlled oscillator signal in an analog to digital converter; and 
 generating a frequency adjustment value based on the voltage control oscillator signal using the analog to digital converter wherein the frequency adjustment value is used to generate the frequency compensation value. 
 
     
     
       16. The method of  claim 9  wherein the high speed resonator is a resonator selected from the group consisting of a bulk acoustic wave (BAW) resonator, a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR). 
     
     
       17. A phase lock loop that receives a reference signal,
 outputs a high frequency clock signal and feeds back an error correction signal for adding to the reference signal, the phase lock loop comprising: 
 a high frequency oscillator that receives a high frequency signal and generates a reference clock signal; 
 a low frequency oscillator that receives the low frequency signal and generates a stable clock signal; 
 a frequency ratio estimator that determines a ratio between the reference clock signal and the stable clock signal; and 
 a fractional N divider that receives a signal indicating the ratio between the reference clock signal and stable clock signal and an output signal of the PLL and generates an error feedback correction based upon the ratio of the reference clock signal to the stable clock signal; and 
 a crystal resonator that generates a low frequency signal and provides the low frequency signal to the low frequency oscillator. 
 
     
     
       18. The phase locked loop of  claim 17  further comprising:
 a high frequency resonator that generates the high frequency signal and provides the high frequency signal to the oscillator. 
 
     
     
       19. The phase locked loop of  claim 18  wherein the high speed resonator is a resonator selected from the group consisting of a bulk acoustic wave (BAW) resonator, a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR). 
     
     
       20. The phase lock loop of  claim 17  wherein the high frequency clock signal output by the phase locked loop has a frequency that is N times a frequency of the stable clock signal. 
     
     
       21. The phase lock loop of  17  further comprising:
 a delta sigma modulator that receives the output from the frequency ratio estimator and generates a control signal for the fractional N divider. 
 
     
     
       22. The phase lock loop of  claim 17  further comprising:
 a phase detector that receives the reference clock signal and the error correction signal and generates a corrected reference clock signal; 
 a loop filter that receive the corrected reference clock signal and outputs a control signal; 
 a voltage controlled oscillator that receives the control signal from the loop filter and generates a high frequency clock signal. 
 
     
     
       23. A method for generating a high frequency clock signal comprising:
 generating a reference signal using a high frequency oscillator; 
 generating a stable signal using a low frequency oscillator; 
 receiving the reference clock signal and an error correction signal in a phase detector; 
 generating a corrected reference clock signal from the reference clock signal and the error correction signal using the phase detector; 
 receiving the corrected reference clock signal in a loop filter; 
 generating a voltage control signal from the corrected reference clock signal using the loop filter; 
 receiving the voltage control signal in a voltage control oscillator; 
 generating a high frequency clock signal from the voltage control signal using the voltage controlled oscillator; 
 determining a ratio between the reference signal and the stable signal using a frequency ratio estimator; and 
 controlling a fractional N divider using the ratio between the reference signal and the stable signal to generate the corrected error signal from the high frequency clock signal generated by the voltage controlled oscillator. 
 
     
     
       24. The method of  claim 23  further comprising:
 generating the high frequency signal using a high frequency resonator and providing the high frequency signal to the high frequency oscillator. 
 
     
     
       25. The method of  claim 24  wherein the high speed resonator is a resonator selected from the group consisting of a bulk acoustic wave (BAW) resonator, a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR). 
     
     
       26. The method of  claim 23  further comprising:
 generating the low frequency signal using a crystal oscillator and providing the low frequency signal to the low frequency oscillator. 
 
     
     
       27. The method of  claim 23  wherein the high frequency clock signal output by the voltage controlled oscillator has a frequency that is N times a frequency of the stable clock signal.